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| KM416RD8AS Target Direct RDRAMTM 128Mbit RDRAM 256K x 16 bit x 2*16 Dependent Banks for Consumer Package Direct RDRAMTM Revision 0.9 July 1999 Rev. 0.9 July 1999 KM416RD8AS Revision History Version 0.9 (July 1999) -Target - Based on the Rambus Datasheet ver. 0.9. - For Consumer Package. Target Direct RDRAMTM Rev. 0.9 July 1999 KM416RD8AS ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 Target Direct RDRAMTM KM 4 XX XX XX X X - X X XX SAMSUNG Memory Device Organization Product Density Speed tRAC(Row Access Time) Power & Refresh Package Type Revision 1. SAMSUNG Memory 2. Device - 4 : DRAM 7. Package Type - C : u - BGA(CSP-Forward) - D : u - BGA(CSP-Reverse) - W : WL - CSP - S : u-BGA For Consumer Package 3. Organization - 16 : x16 bit - 18 : x18 bit 8. Power & Refresh - Blank : Normal Power Self Refesh(32m/8K, 3.9us) -L : Low Power Self Refesh(32m/8K, 3.9us) -R : Normal Power Self Refesh(32m/16K, 1.9us) -S : Low Power Self Refesh(32m/16K, 1.9us) 4. Product - RD : Direct RAMBUS DRAM 5. Density - 2 : 2M - 4 : 4M - 8 : 8M - 16 : 16M 9. tRAC(Row Access Time) - Blank : for Daisy Chain Sample -M : 40ns -K : 45ns -G : 53.3ns - B~D, F, J, L, N~ : Reserved 6. Revision - Blank : 1st Gen. -A : 2nd Gen. 10. Speed - DS : for Daisy Chain Sample - 80 : 800Mbps (400MHz) - 70 : 711Mbps (356MHz) - 60 : 600Mbps (300MHz) Rev. 0.9 July 1999 KM416RD8AS Overview The Rambus Direct RDRAMTM is a general purpose highperformance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 128Mbit Direct Rambus DRAMs (RDRAM(R)) ar extremely high-speed CMOS DRAMs organized as 8M words by 16 bits. The use of Rambus Signaling Level (RSL) technology permits 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking. Target Direct RDRAMTM KM4xx RD8AC SEC KOREA SEC KOREA KM416RD8AS-RK80 Figure 1: Direct RDRAM Consumer CSP Package Key Timing Parameters/Part Numbers Speed Organization Binning 256Kx16x32sa -RM80 -SM80 I/O Freq. MHz 800 800 trac (Row Access Time) ns 40 40 Part Number Features Highest sustained bandwidth per DRAM device KM416RD8AS-R bM80 KM416RD8AS-SCM80 - 1.6GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simultaneously at full bandwidth data rates Low latency features a.The "32s"designation indicates that this RDRAM core is composed of 32 banks which use a "split" bank architecture. b.The "R"designation indicates that this RDRAM core uses Normal Power Self Refresh. c.The "S"designation indicates that this RDRAM core uses Low Power Self Refresh. - Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions Advanced power management: - Multiple low power states allows flexibility in powerconsumption versus time to transition to active state - Power-down self-refresh Organization: 1Kbyte pages and 32 banks, x 16 Uses Rambus Signaling Level (RSL) for up to 800MHz operation The 128Mbit Direct RDRAMs are offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAMs operate from a 2.5 volt supply. Page 1 Rev. 0.9 July 1999 KM416RD8AS Pinouts and Definitions This table shows the pin assignments of the center-bondedforward RDRAM package from the top-side of the package Table 1 : Pin Assignment (Top View) 7 6 5 4 3 2 1 SCK VCMOS NC VSS DQA6 DQA3 VDD DQA1 DQA0 VSS VREF CTMN VSS RQ7 CTM VDD RQ1 RQ4 VSS DQB2 RQ0 VSS DQB6 DQB3 SIO1 VCMOS NC DQA7 VSS CMD DQA4 DQA5 VDD CFM DQA2 VSS CFMN VDDA VSSA RQ5 RQ6 VDD RQ3 RQ2 VSS DQB0 DQB1 VDD DQB4 DQB5 VDD DQB7 VSS SIO0 Target Direct RDRAMTM (the view looking down on the package as it is mounted on the circuit board). A B C D E F G H J Top View Top marking example of Consumer package SEC CKOREA E A SE KOR KM416RD8AS-RK80 KM4xxRD8AC Chip For Consumer package, pin #1(ROW 1, COL A) is located at the A1 postion on the top side and the A1 position is marked by the marker "*" Page 2 Rev. 0.9 July 1999 KM416RD8AS Table 2: Pin Description Signal SIO1,SIO0 I/O I/O Type CMOSa # of Pins 2 Description Target Direct RDRAMTM Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. Serial clock input. Clock source used for reading from and writing to the control registers Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Eight pins which carry a byte of read or write data between the Channel and the RDRAM. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity Logic threshold reference voltage for RSL signals Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Row access control. Three pins containing control and address information for row accesses. Column access control. Five pins containing control and address information for column accesses. Data byte B. Eight pins which carry a byte of read or write data between the Channel and the RDRAM. No Connection CMD I CMOSa 1 SCK I CMOSa 1 VDD VDDa VCMOS GND GNDa DQA7..DQA0 I/O RSL b RSL b RSL b 6 1 2 9 1 8 CFM I 1 CFMN I 1 VREF CTMN I RSL b RSL b RSL b RSL b RSL b 1 1 CTM I 1 RQ7..RQ5 or ROW2..ROW0 RQ4..RQ0 or COL4..COL0 DQB7.. DQB0 NC I 3 I 5 I/O 8 2 54 Total pin count per package a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero. Page 3 Rev. 0.9 July 1999 KM416RD8AS Target Direct RDRAMTM DQB7..DQB0 8 RQ7..RQ5 or ROW2..ROW0 3 CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN 2 RCLK 2 RQ4..RQ0 or COL4..COL0 5 DQA7..DQA0 8 RCLK 1:8 Demux TCLK Packet Decode ROWR ROWA 11 5 5 9 ROP DR BR AV Match 1:8 Demux RCLK Control Registers 6 REFR Power Modes COLX 5 5 Packet Decode COLC 5 5 5 6 C 8 COLM 8 R DEVID XOP DX BX COP DC BC M S Match XOP Decode Match MB MA Mux Row Decode DM Write Buffer Mux Mux PRER ACT Sense Amp 32x64 SAmp SAmp SAmp PREX Column Decode & Mask DRAM Core 32x64 512x64x128 Bank 0 32x64 0 64 SAmp SAmp SAmp PREC RD, WR Internal DQB Data Path 0 64 Internal DQA Data Path 0/1 0/1 64 Bank 1 1/2 1/2 Bank 2 *** 64 RCLK 8 8 *** 8 *** 8 RCLK SAmp SAmp SAmp 14/15 13/14 Bank 13 Bank 14 Bank 15 13/14 14/15 15 SAmp SAmp SAmp Write Buffer 1:8 Demux Write Buffer 1:8 Demux 8 8 SAmp SAmp SAmp 15 SAmp SAmp SAmp 17/18 16/17 16 16 Bank 16 Bank 17 Bank 18 *** 16/17 17/18 TCLK 8 8 TCLK *** 8:1 Mux *** 8:1 Mux 8 8 SAmp SAmp SAmp 30/31 29/30 Bank 29 Bank 30 Bank 31 SAmp SAmp SAmp 29/30 30/31 31 Figure 2: 128 Mbit Direct RDRAM Block Diagram 31 Page 4 Rev. 0.9 July 1999 KM416RD8AS General Description Figure 2 is a block diagram of the 128 Mbit Direct RDRAM. It consists of two major blocks: a "core" block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6GB/s. Target Direct RDRAMTM 24-bit ROWA (row-activate) or ROWR (row-operation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. Control Registers: The CMD, SCK, SIO0, and SIO1 pins appear in the upper center of Figure 2. They are used to write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The nine bit REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 256 byte sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. RD Command: The RD (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. WR Command: The WR (write) command causes a dualoct received from the DQA/DQB data pins of the Channel to be loaded into the write buffer. There is also space in the write buffer for the BC bank address and C column address information. The data in the write buffer is automatically retired (written with optional bytemask) to one of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD, WR, or NOCOP to another device, or during a WR or NOCOP to the same device. The write buffer will not retire during a RD to the same device. The write buffer reduces the delay needed for the internal DQA/DQB data path turnaround. DQA,DQB Pins: These 16 pins carry read (Q) and write (D) data across the Channel. They are multiplexed/de-multiplexed from/to two 64-bit data paths (running at one-eighth the data frequency) inside the RDRAM. Banks: The 16Mbyte core of the RDRAM is divided into sixteen 0.5Mbyte banks, each organized as 512 rows, with each row containing 64 dualocts, and each dualoct containing 16 bytes. A dualoct is the smallest unit of data that can be addressed. Sense Amps: The RDRAM contains two sets of 17 sense amps. Each sense amp consists of 512 bytes of fast storage (256 for DQA and 256 for DQB) and can hold one-half of one row of one bank of the RDRAM. The sense amp may hold any of the 512 half-rows of an associated bank. However, each sense amp is shared between two adjacent banks of the RDRAM (except for numbers 0, 15, 16, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed. PREC Precharge: The NOP, RDA and WRA commands are similar to PREC, RD and WR, except that a precharge operation is scheduled at the end of the data transfer. These commands provide a second mechanism for performing precharge. PREX Precharge: After a RD command, or after a WR command with no byte masking (M=0), a COLX packet may be used to specify an extended operation (XOP). The most important XOP command is PREX. This command provides a third mechanism for performing precharge. RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also called ROW2..ROW0, and are used primarily for controlling row accesses. RQ4..RQ0 are also called COL4..COL0, and are used primarily for controlling column accesses. ROW Pins: The principle use of these three pins is to manage the transfer of data between the banks and the sense amps of the RDRAM. These pins are de-multiplexed into a Page 5 Rev. 0.9 July 1999 KM416RD8AS Packet Format Figure 3 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 4 describes the fields which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM. Target Direct RDRAMTM The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and ROWR packet provide a five bit device address and a five bit bank address. An ROWA packet uses the remaining bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field. Note the use of the "RsvX" notation to reserve bits for future address field extension. Table 4: Field Description for ROWA Packet and ROWR Packet Field DR4T,DR4F DR3..DR0 BR4..BR0 AV R7..R0 ROP10..ROP0 Description Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit. Device address for ROWA or ROWR packet. Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM. Selects between ROWA packet (AV=1) and ROWR packet (AV=0). Row address for ROWA packet. RsvR denotes bits reserved for future row address extension. Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions. Figure 3 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 5 describes the fields which comprise these packets. The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and is also framed by the S bit. The 23 bit COLC packet has a five bit device address, a five bit bank address, a six bit column address, and a four bit opcode. The COLC packet specifies a read or write command, as well as some power management commands. The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a time t RTR earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device address, a five bit bank address, and a five bit opcode. The COLX packet may also be used to specify some housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not otherwise associated with any other packet. Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet Field S DC4..DC0 BC4..BC0 C5..C0 COP3..COP0 M MA7..MA0 MB7..MB0 DX4..DX0 BX4..BX0 XOP4..XOP0 Description Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets. Device address for COLC packet. Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0's). Column address for COLC packet. RsvC denotes bits ignored by the RDRAM. Opcode field for COLC packet. Specifies read, write, precharge, and power management functions. Selects between COLM packet (M=1) and COLX packet (M=0). Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA7..0. Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB7..0. Device address for COLX packet. Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0's). Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions. Page 6 Rev. 0.9 July 1999 KM416RD8AS Target Direct RDRAMTM T0 T1 T2 T3 T8 T9 T10 T11 CTM/CFM CTM/CFM ROW2 DR4T DR2 BR0 BR3 RsvR R8 ROW1 ROW0 DR4F DR1 BR1 BR4 RsvR R7 R5 R2 ROW2 DR4T DR2 BR0 BR3 ROW1 ROW0 ROP10 ROP8 ROP5 ROP2 R4 R3 R1 R0 DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1 DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0 DR3 DR0 BR2 RsvB AV=1 R6 ROWA Packet T0 T1 T2 T3 ROWR Packet T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 9 T 10 T 11 T12 T13 T14 T15 CTM/CFM DC4 DC3 DC2 COP1 DC1 COP0 DC0 COP2 S=1 RsvC C5 RsvB BC2 BC4 BC1 COP3 BC3 BC0 C4 C3 C2 C1 C0 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 PRER c0 COL4 COL3 COL2 COL1 COL0 tPACKET WR b1 MSK (b1) PREX d0 COLC Packet T8 T9 T10 T11 T12 T13 T14 T15 CTM/CFM CTM/CFM COL4 COL3 COL2 COL1 COL0 a S=1a MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 COL4 COL3 COL2 COL1 COL0 S=1b DX4 XOP4 RsvB BX1 M=0 DX3 XOP3 BX4 BX0 DX2 XOP2 BX3 DX1 XOP1 BX2 DX0 XOP0 b The The COLM is associated with a previous COLC, and is aligned with the present COLC, indicated by the Start bit (S=1) position. COLM Packet Figure 3: Packet Formats COLX Packet COLX is aligned with the present COLC, indicated by the Start bit (S=1) position. Page 7 Rev. 0.9 July 1999 KM416RD8AS Field Encoding Summary Table 6 shows how the six device address bits are decoded for the ROWA and ROWR packets. The DR4T and DR4F encoding merges a fifth device bit with a framing bit. When neither bit is asserted, the device is not selected. Note that a Target Direct RDRAMTM broadcast operation is indicated when both bits are set. Broadcast operation would typically be used for refresh and power management commands. If the device is selected, the DM (DeviceMatch) signal is asserted and an ACT or ROP command is performed. Table 6: Device Field Encodings for ROWA Packet and ROWR Packet DR4T 1 0 1 0 DR4F 1 1 0 0 Device Selection All devices (broadcast) One device selected One device selected No packet present Device Match signal (DM) DM is set to 1 DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0 DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0 DM is set to 0 Table 7 shows the encodings of the remaining fields of the ROWA and ROWR packets. An ROWA packet is specified by asserting the AV bit. This causes the specified row of the specified bank of this device to be loaded into the associated sense amps. An ROWR packet is specified when AV is not asserted. An 11 bit opcode field encodes a command for one of the banks of this device. The PRER command causes a bank and its two associated sense amps to precharge, so another row or an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the row address comes from an internal register REFR, and REFR is incremented at the largest bank address. The REFP (refresh-precharge) command is identical to a PRER command. The NAPR, NAPRC, PDNR, ATTN, and RLXR commands are used for managing the power dissipation of the RDRAM and are described in more detail in " Power state management " on page 38. The TCEN and TCAL commands are used to adjust the output driver slew rate and they are described in more detail in "Current and Temperature Control" on page 43. Table 7: ROWA Packet and ROWR Packet Field Encodings ROP10..ROP0 Field DMa 0 1 1 1 1 1 1 1 1 1 1 1 1 AV 10 1 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2:0 --ACT 0 1 0 0 0 0 x x 0 0 0 0 1 1 0 0 0 x x 0 0 0 xc 0 0 0 1 1 x x 0 0 0 x 0 0 1 0 1 x x 0 0 0 x x x x x x 0 1 x x 0 000 000 000 000 000 000 000 000 001 010 000 PRER REFA REFP PDNR NAPR NAPRC ATTNb RLXR TCAL TCEN NOROP No operation. Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb. Precharge bank BR4..BR0 of this device. Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device. Increment REFR if BR4..BR0 = 1111 (see Figure 50). Precharge bank BR4..BR0 of this device after REFA (see Figure 50). Move this device into the powerdown (PDN) power state (see Figure 47). Move this device into the nap (NAP) power state (see Figure 47). Move this device into the nap (NAP) power state conditionally Move this device into the attention (ATTN) power state (see Figure 45). Move this device into the standby (STBY) power state (see Figure 46). Temperature calibrate this device (see Figure 52). Temperature calibrate/enable this device (see Figure 52). No operation. Name Command Description Row address 1 0 1 x x x x x 0 0 0 1 0 0 x x x x x 0 0 0 0 0 1 0 0 0 x x 0 0 0 a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 6. b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1). c. An " x " entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000). Page 8 Rev. 0.9 July 1999 KM416RD8AS Table 8 shows the COP field encoding. The device must be in the ATTN power state in order to receive COLC packets. The COLC packet is used primarily to specify RD (read) and WR (write) commands. Retire operations (moving data from the write buffer to a sense amp) happen automatically. See Figure 17 for a more detailed description. Target Direct RDRAMTM The COLC packet can also specify a PREC command, which precharges a bank and its associated sense amps. The RDA/WRA commands are equivalent to combining RD/WR with a PREC. RLXC (relax) performs a power mode transition. See " Power State Management " on page 38. Table 8: COLC Packet Field Encodings S DC4.. DC0 (select device)a ---/= (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) COP3..0 Name --------x000b x001 x010 x011 x100 x101 x110 x111 1xxx NOCOP WR RSRV RD PREC WRA RSRV RDA RLXC Command Description No operation. Retire write buffer of this device. Retire write buffer of this device. Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer. Reserved, no operation. Read column C5..C0 of bank BC4..BC0 of this device. Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 14). Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired. Reserved, no operation. Same as RD, but precharge bank BC4..BC0 afterward. Move this device into the standby (STBY) power state (see Figure 46). 0 1 1 1 1 1 1 1 1 1 1 a. " /= " means not equal, " == " means equal. b. An " x " entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value (1001). Table 9 shows the COLM and COLX field encodings. The M bit is asserted to specify a COLM packet with two 8 bit bytemask fields MA and MB. If the M bit is not asserted, an COLX is specified. It has device and bank address fields, and an opcode field. The primary use of the COLX packet is to permit an independent PREX (precharge) command to be specified without consuming control bandwidth on the ROW pins. It is also used for the CAL(calibrate) and SAM (sample) current control commands (see "Current and Temperature Control" on page 43), and for the RLXX power mode command (see "Power State Management" on page 38). Table 9: COLM Packet and COLX Packet Field Encodings M 1 0 0 0 0 0 0 0 DX4 .. DX0 (selects device) ---/= (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) == (DEVID4 ..0) XOP4..0 00000 1xxx0a x10x0 x11x0 xxx10 xxxx1 Name MSK NOXOP PREX CAL CAL/SAM RLXX RSRV Command Description MB/MA bytemasks used by WR/WRA. No operation. No operation. Precharge bank BX4..BX0 of this device (see Figure 14). Calibrate (drive) IOL current for this device (see Figure 51). Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 51). Move this device into the standby (STBY) power state (see Figure 46). Reserved, no operation. a. An "x" entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010). Page 9 Rev. 0.9 July 1999 KM416RD8AS DQ Packet Timing Figure 4 shows the timing relationship of COLC packets with D and Q data packets. This document uses a specific convention for measuring time intervals between packets: all packets on the ROW and COL pins (ROWA, ROWR, COLC, COLM, COLX) use the trailing edge of the packet as a reference point, and all packets on the DQA/DQB pins (D and Q) use the leading edge of the packet as a reference point. An RD or RDA command will transmit a dualoct of read data Q a time tCAC later. This time includes one to five cycles of round-trip propagation delay on the Channel. The tCAC parameter may be programmed to a one of a range of values ( 8, 9, 10, 11, or 12 tCYCLE). The value chosen depends upon the number of RDRAM devices on the Channel and the RDRAM timing bin. See Figure 39 for more information. Target Direct RDRAMTM A WR or WRA command will receive a dualoct of write data D a time tCWD later. This time does not need to include the round-trip propagation time of the Channel since the COLC and D packets are traveling in the same direction. When a Q packet follows a D packet (shown in the left half of the figure), a gap (tCAC -tCWD) will automatically appear between them because the tCWD value is always less than the tCAC value. There will be no gap between the two COLC packets with the WR and RD commands which schedule the D and Q packets. When a D packet follows a Q packet (shown in the right half of the figure), no gap is needed between them because the tCWD value is less than the tCAC value. However, , a gap of tCAC -t CWD or greater must be inserted between the COLC packets with the RD WR commands by the controller so the Q and D packets do not overlap. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM This gap on the DQA/DQB pins appears automatically This gap on the COL pins must be inserted by the controller ROW2 ..ROW0 tCWD COL4 ..COL0 DQA7..0 DQB7..0 tCAC WR a1 RD b1 tCAC -tCWD *** tCAC-tCWD WR d1 WR d1 WR d1 WR d1 WR d1 *** tCWD *** RD c1 Q (b1) Q (b1) Q (a1) Q (a1) Q (a1) D (a1) Q (c1) D (d1) Q (c1) D (d1) Q (c1) D (d1) Q (c1) D (d1) Q (a1) D (d1) *** *** tCAC Figure 4: Read (Q) and Write (D) Data Packet - Timing for tCAC = 8, 9, 10, 11, or 12 tCYCLE COLM Packet to D Packet Mapping Figure 5 shows a write operation initiated by a WR command in a COLC packet. If a subset of the 16 bytes of write data are to be written, then a COLM packet is transmitted on the COL pins a time tRTR after the COLC packet containing the WR command. The M bit of the COLM packet is set to indicate that it contains the MA and MB mask fields. Note that this COLM packet is aligned with the COLC packet which causes the write buffer to be retired. See Figure 17 for more details. If all 16 bytes of the D data packet are to be written, then no further control information is required. The packet slot that would have been used by the COLM packet (tRTR after the COLC packet) is available to be used as an COLX packet. This could be used for a PREX precharge command or for a housekeeping command (this case is not shown). The M bit is not asserted in an COLX packet and causes all 16 bytes of the previous WR to be written unconditionally. Note that a RD command will never need a COLM packet, and will always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits). Figure 5 also shows the mapping between the MA and MB fields of the COLM packet and bytes of the D packet on the DQA and DQB pins. Each mask bit controls whether a byte of data is written (=1) or not written (=0). Page 10 Rev. 0.9 July 1999 KM416RD8AS Target Direct RDRAMTM T0 T 1 T 2 T 3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T 17 T 18 T 19 T20 T 21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T 33 T 34 T 35 T36 T 37 T 38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Transaction a: WR a0 = {Da,Ba,Ra} ACT a0 PRER a2 ACT b0 tRTR WR a1 retire (a1) MSK (a1) tCWD D (a1) a1 = {Da,Ba,Ca1} a3 = {Da,Ba} COLM Packet T17 T18 T19 T20 T19 D Packet T20 T21 T22 CTM/CFM CTM/CFM COL4 COL3 COL2 COL1 COL0 MA7 MA5 MA3 MA1 M=1 MA6 MA4 MA2 MA0 MB7 MB4 MB1 MB6 MB3 MB0 MB5 MB2 DQB7 DQB6 *** DB7 DB15 DB23 DB31 DB39 DB47 DB55 DB63 DB6 DB14 DB22 DB30 DB38 DB46 DB54 DB62 DQB1 DQB0 DB1 DB9 DB17 DB25 DB33 DB41 DB49 DB57 DB0 DB8 DB16 DB24 DB32 DB40 DB48 DB56 MB0 Each bit of the MB7..MB0 field controls writing (=1) or no writing (=0) of the indicated DB bits when the M bit of the COLM packet is one. When M=1, the MA and MB fields control writing of individual data bytes. When M=0, all data bytes are written unconditionally. MB1 MB2 MB3 MB4 MB5 MB6 MB7 DQA7 DQA6 *** DA7 DA15 DA23 DA31 DA49 DA47 DA55 DA63 DA6 DA14 DA22 DA30 DA38 DA46 DA54 DA62 DQA1 Each bit of the MA7..MA0 field controls writing (=1) or no writing (=0) of the indicated DA bits when the M bit of the COLM packet is one. DA1 DA9 DA17 DA25 DA33 DA41 DA49 DA56 DQA0 DA0 DA8 DA16 DA24 DA32 DA40 DA48 DA56 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 Figure 5: Mapping Between COLM Packet and D Packet for WR Command Page 11 Rev. 0.9 July 1999 KM416RD8AS ROW-to-ROW Packet Interaction T0 T 1 T 2 T 3 T4 T 5 T 6 T 7 T8 T 9 T 10 T 11 T12 T13 T14 T15 T16 T 17 T 18 T 19 T Target Direct RDRAMTM Cases RR1 through RR4 show two successive ACT commands. In case RR1, there is no restriction since the ACT commands are to different devices. In case RR2, the tRR restriction applies to the same device with non-adjacent banks. Cases RR3 and RR4 are illegal (as shown) since bank Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1 is inserted, t RRDELAY is tRC (t RAS to the PRER command, and tRP to the next ACT). Cases RR5 through RR8 show an ACT command followed by a PRER command. In cases RR5 and RR6, there are no restrictions since the commands are to different devices or to non-adjacent banks of the same device. In cases RR7 and RR8, the t RAS restriction means the activated bank must wait before it can be precharged. CTM/CFM tRRDELAY ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Transaction a: ROPa Transaction b: ROPb a0 = {Da,Ba,Ra} b0= {Db,Bb,Rb} ROPa a0 ROPb b0 Figure 6: ROW-to-ROW Packet Interaction- Timing Figure 6 shows two packets on the ROW pins separated by an interval tRRDELAY which depends upon the packet contents. No other ROW packets are sent to banks {Ba,Ba+1,Ba-1} between packet "a" and packet "b" unless noted otherwise. Table 10 summarizes the tRRDELAY values for all possible cases. Cases RR9 through RR12 show a PRER command followed by an ACT command. In cases RR9 and RR10, there are essentially no restrictions since the commands are to different devices or to non-adjacent banks of the same device. RR10a and RR10b depend upon whether a bracketed bank (Ba+-1) is precharged or activated. In cases RR11 and RR12, the same and adjacent banks must all wait t RP for the sense amp and bank to precharge before being activated. Table 10: ROW-to-ROW Packet Interaction - Rules Case # RR1 RR2 RR3 RR4 RR5 RR6 RR7 RR8 RR9 RR10 RR10a RR10b RR11 RR12 RR13 RR14 RR15 RR16 ROPa ACT ACT ACT ACT ACT ACT ACT ACT PRER PRER PRER PRER PRER PRER PRER PRER PRER PRER Da Da Da Da Da Da Da Da Da Da Da Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra ROPb ACT ACT ACT ACT PRER PRER PRER PRER ACT ACT ACT ACT ACT ACT PRER PRER PRER PRER Db /= Da == Da == Da == Da /= Da == Da == Da == Da /= Da == Da == Da == Da == Da == Da /= Da == Da == Da == Da Bb xxxx /= {Ba,Ba+1,Ba-1} == {Ba+1,Ba-1} == {Ba} xxxx /= {Ba,Ba+1,Ba-1} == { Ba+1,Ba-1} == {Ba} xxxx /= {Ba,Ba+-1,Ba+-2} == {Ba+2} == {Ba-2} == {Ba+1,Ba-1} == {Ba} xxxx /= {Ba,Ba+1,Ba-1} == {Ba+1,Ba-1} == Ba Rb x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x tRRDELAY tPACKET tRR tRC - illegal unless PRER to Ba/Ba+1/Ba-1 tRC - illegal unless PRER to Ba/Ba+1/Ba-1 tPACKET tPACKET tRAS tRAS tPACKET tPACKET tPACKET /tRP if Ba+1 is precharged/activated. tPACKET /tRP if Ba-1 is precharged/activated. tRP tRP tPACKET tPP tPP tPP Figure 10 Figure 10 Figure 12 Figure 12 Figure 12 Figure 12 Example Figure 11 Figure 11 Figure 10 Figure 10 Figure 11 Figure 11 Figure 10 Figure 15 Figure 12 Figure 12 Page 12 Rev. 0.9 July 1999 KM416RD8AS ROW-to-ROW Interaction - continued Cases RR13 through RR16 summarize the combinations of two successive PRER commands. In case RR13 there is no restriction since two devices are addressed. In RR14, tPP applies, since the same device is addressed. In RR15 and RR16, the same bank or an adjacent bank may be given repeated PRER commands with only the tPP restriction. Two adjacent banks can't be activate simultaneously. A precharge command to one bank will thus affect the state of the adjacent banks (and sense amps). If bank Ba is activate and a PRER is directed to Ba, then bank Ba will be precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If bank Ba+1 is activate and a PRER is directed to Ba, then bank Ba+1 will be precharged along with sense amps Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a PRER is directed to Ba, then bank Ba-1 will be precharged along with sense amps Ba/Ba-1 and Ba-1/Ba-2. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN, TCAL, and TCEN commands are discussed in later sections (see Table 7 for cross-ref). Target Direct RDRAMTM Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure 15 and Figure 16 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets. T0 T 1 T 2 T 3 T4 T 5 T 6 T 7 T8 T 9 T 10 T 11 T12 T13 T14 T15 T16 T 17 T 18 T 19 T CTM/CFM tRCDELAY ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Transaction a: ROPa Transaction b: COPb a0 = {Da,Ba,Ra} b1= {Db,Bb,Cb1} ROPa a0 COPb b1 Figure 7: ROW-to-COL Packet Interaction- Timing Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9). The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent PRER command constraints using the rules summarized in Figure 14. ROW-to-COL Packet Interaction Figure 7 shows two packets on the ROW and COL pins. They must be separated by an interval tRCDELAY which depends upon the packet contents. Table 11 summarizes the tRCDELAY values for all possible cases. Note that if the COL packet is earlier than the ROW packet, it is considered a COL-to-ROW packet interaction. Table 11: ROW-to-COL Packet Interaction - Rules Case # RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 ROPa ACT ACT ACT ACT ACT PRER PRER PRER PRER Da Da Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ra Ra Ra Ra Ra Ra Ra Ra Ra Ra COPb NOCOP,RD,retire NOCOP RD,retire RD,retire RD,retire NOCOP,RD,retire NOCOP RD,retire RD,retire Db /= Da == Da == Da == Da == Da /= Da == Da == Da == Da Bb xxxx xxxx /= {Ba,Ba+1,Ba-1} == {Ba+1,Ba-1} == Ba xxxx xxxx /= {Ba,Ba+1,Ba-1} == {Ba+1,Ba-1} Cb1 x..x x..x x..x x..x x..x x..x x..x x..x x..x tRCDELAY 0 0 0 Illegal tRCD 0 0 0 Illegal Figure 15 Example Page 13 Rev. 0.9 July 1999 KM416RD8AS COL-to-COL Packet Interaction T0 T 1 T 2 T 3 T4 T 5 T 6 T 7 T8 T 9 T 10 T 11 T12 T13 T14 T15 T16 T 17 T 18 T 19 T Target Direct RDRAMTM CC2, CC4, and CC5, there is no restriction (t CCDELAY is tCC). In cases CC6 through CC10, COPb is a WR command and COPc is a RD command. The t CCDELAY value needed between these two packets depends upon the command and address in the packet with COPa. In particular, in case CC6 when there is WR-WR-RD command sequence directed to the same device, a gap will be needed between the packets with COPb and COPc. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Figure 18 (right) provides a more detailed explanation of this case. In case CC10, there is a RD-WR-RD sequence directed to the same device. If a prior write to the same device is unretired when COPa is issued, then a gap will be needed between the packets with COPb and COPc as in case CC6. The gap will need a COLC packet with a NOCOP command directed to any device in order to force an automatic retire to take place. Cases CC7, CC8, and CC9 have no restriction (t CCDELAY is tCC). For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation PREC to take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 14. CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Transaction a: COPa Transaction b: COPb Transaction c: COPc a1 = {Da,Ba,Ca1} b1 = {Db,Bb,Cb1} c1 = {Dc,Bc,Cc1} tCCDELAY COPa a1 COPb b1 COPc c1 Figure 8: COL-to-COL Packet Interaction- Timing Figure 8 shows three arbitrary packets on the COL pins. Packets "b" and "c" must be separated by an interval tCCDELAY which depends upon the command and address values in all three packets. Table 12 summarizes the tCCDELAY values for all possible cases. Cases CC1 through CC5 summarize the rules for every situation other than the case when COPb is a WR command and COPc is a RD command. In CC3, when a RD command is followed by a WR command, a gap of tCAC -tCWD must be inserted between the two COL packets. See Figure 4 for more explanation of why this gap is needed. For cases CC1, Table 12: COL-to-COL Packet Interaction - Rules Case # CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CC10 COPa xxxx xxxx xxxx xxxx xxxx WR WR WR NOCOP RD Da xxxxx xxxxx xxxxx xxxxx xxxxx == Db == Db /= Db == Db == Db Ba x..x x..x x..x x..x x..x x x x x x Ca1 x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x COPb NOCOP RD,WR RD RD WR WR WR WR WR WR Db Db Db Db Db Db Db Db Db Db Db Bb Bb Bb Bb Bb Bb Bb Bb Bb Bb Bb Cb1 Cb1 Cb1 Cb1 Cb1 Cb1 Cb1 Cb1 Cb1 Cb1 Cb1 COPc xxxx NOCOP WR RD WR RD RD RD RD RD Dc xxxxx xxxxx xxxxx xxxxx xxxxx == Db /= Db == Db == Db == Db Bc x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x Cc1 x..x x..x x..x x..x x..x x..x x..x x..x x..x x..x tCCDELAY tCC tCC tCC+tCAC -tCWD tCC tCC tRTR tCC tCC tCC tCC Figure 4 Figure 15 Figure 16 Figure 18 Example Page 14 Rev. 0.9 July 1999 KM416RD8AS COL-to-ROW Packet Interaction T0 T 1 T 2 T 3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T 17 T 18 T 19 T Target Direct RDRAMTM Case CR4 is illegal because an already-activated bank is to be re-activated without being precharged Case CR5 is illegal because an adjacent bank can't be activated or precharged until bank Ba is precharged first. In case CR6, the COLC packet contains a RD command, and the ROW packet contains a PRER command for the same bank. The t RDP parameter specifies the required spacing. Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a PRER command for the same bank. The t RTP parameter specifies the required spacing. Case CR8 is labeled "Hazardous" because a WR command should always be followed by an automatic retire before a precharge is scheduled. Figure 19 shows an example of what can happen when the retire is not able to happen before the precharge. For the purposes of analyzing COL-to-ROW interactions, the PREC, WRA, and RDA commands of the COLC packet are equivalent to the NOCOP, WR, and RD commands. These commands also cause a precharge operation to take place. This precharge may converted to an equivalent PRER command on the ROW pins using the rules summarized in Figure 14. A ROW packet may contain commands other than ACT or PRER. The REFA and REFP commands are equivalent to ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR commands are discussed in a later section. CTM/CFM tCRDELAY ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Transaction a: COPa Transaction b: ROPb a1= {Da,Ba,Ca1} b0= {Db,Bb,Rb} COPa a1 ROPb b0 Figure 9: COL-to-ROW Packet Interaction- Timing Figure 9 shows arbitrary packets on the COL and ROW pins. They must be separated by an interval tCRDELAY which depends upon the command and address values in the packets. Table 13 summarizes the tCRDELAY value for all possible cases. Cases CR1, CR2, CR3, and CR9 show no interaction between the COL and ROW packets, either because one of the commands is a NOP or because the packets are directed to different devices or to non-adjacent banks. Table 13: COL-to-ROW Packet Interaction - Rules Case # CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 COPa NOCOP RD/WR RD/WR RD/WR RD/WR RD retire a WRb xxxx Da Da Da Da Da Da Da Da Da Da Ba Ba Ba Ba Ba Ba Ba Ba Ba Ba Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 Ca1 ROPb x..x x..x x..x ACT ACT PRER PRER PRER NOROP Db xxxxx /= Da == Da == Da == Da == Da == Da == Da xxxxx Bb xxxx xxxx /= {Ba,Ba+1,Ba-1} == {Ba} == {Ba+1,Ba-1} Rb x..x x..x x..x x..x x..x tCRDELAY 0 0 0 Illegal Illegal tRDP tRTP 0 0 Figure 15 Figure 16 Figure 19 Example == {Ba,Ba+1,Ba-1} x..x == {Ba,Ba+1,Ba-1} x..x == {Ba,Ba+1,Ba-1} x..x xxxx x..x a. This is any command which permits the write buffer of device Da to retire (see Table 8). "Ba" is the bank address in the write buffer. b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19. Page 15 Rev. 0.9 July 1999 KM416RD8AS ROW-to-ROW Examples Figure 10 shows examples of some of the ROW-to-ROW packet spacings from Table 10. A complete sequence of activate and precharge commands is directed to a bank. The RR8 and RR12 rules apply to this sequence. In addition to satisfying the tRAS and tRP timing parameters, the separation Target Direct RDRAMTM between ACT commands to the same bank must also satisfy the tRC timing parameter (RR4). When a bank is activated, it is necessary for adjacent banks to remain precharged. As a result, the adjacent banks will also satisfy parallel timing constraints; in the example, the RR11 and RR3 rules are analogous to the RR12 and RR4 rules. a0 = {Da,Ba,Ra} a1 = {Da,Ba+1} b0 = {Da,Ba+1,Rb} b0 = {Da,Ba,Rb} b0 = {Da,Ba+1,Rb} b0 = {Da,Ba,Rb} Same Device Same Device Same Device Same Device Same Device Adjacent Bank Adjacent Bank Same Bank Adjacent Bank Same Bank RR7 RR3 RR4 RR11 RR12 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 tRAS DQA7..0 DQB7..0 tRC Figure 10: Row Packet Example Figure 11 shows examples of the ACT-to-ACT (RR1, RR2) and ACT-to-PRER (RR5, RR6) command spacings from Table 10. In general, the commands in ROW packets may be spaced an interval tPACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. tRP ACT a0 PRER a1 ACT b0 Different Device Same Device Different Device Same Device Any Bank Non-adjacent Bank Any Bank Non-adjacent Bank RR1 RR2 RR5 RR6 a0 = {Da,Ba,Ra} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Figure 11: Row Packet Example ACT a0 ACT b0 ACT a0 ACT c0 ACT a0 PRER b0 ACT a0 PRER c0 tPACKET tRR tPACKET tPACKET Page 16 Rev. 0.9 July 1999 KM416RD8AS Figure 12 shows examples of the PRER-to-PRER (RR13, RR14) and PRER-to-ACT (RR9, RR10) command spacings from Table 10. The RR15 and RR16 cases (PRER-to-PRER to same or adjacent banks) are not shown, but are similar to RR14. In general, the commands in ROW packets may be Target Direct RDRAMTM spaced an interval t PACKET apart unless they are directed to the same or adjacent banks or unless they are a similar command type (both PRER or both ACT) directed to the same device. Different Device Same Device Same Device Same Device Different Device Same Device Any Bank Non-adjacent Bank Adjacent Bank Same Bank Any Bank Non-adjacent Bank RR13 RR14 RR15 RR16 RR9 RR10 a0 = {Da,Ba,Ra} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} c0 = {Da,Ba,Rc} c0 = {Da,Ba+1Rc} b0 = {Db,Bb,Rb} c0 = {Da,Bc,Rc} T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Figure 12: Row Packet Examples PRER a0 PRER b0 PRER a0 PRER c0 PRER a0 ACT b0 PRER a0 ACT c0 tPACKET tPP tPACKET tPACKET Row and Column Cycle Description Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of sensing the value of a bit in a bank's storage cell transfers the bit to the sense amp, but leaves the original bit in the storage cell with an incorrect value. Restore: Because the activation process is destructive, a hidden operation called restore is automatically performed. The restore operation rewrites the bits in the sense amp back into the storage cells of the activated row of the bank. Read/Write: While the restore operation takes place, the sense amp may be read (RD) and written (WR) using column operations. If new data is written into the sense amp, it is automatically forwarded to the storage cells of the bank so the data in the activated row and the data in the sense amp remain identical. Precharge: When both the restore operation and the column operations are completed, the sense amp and bank are precharged (PRE). This leaves them in the proper state to begin another activate operation. Intervals: The activate operation requires the interval tRCD,MIN to complete. The hidden restore operation requires the interval tRAS,MIN - tRCD,MIN to complete. Column read and write operations are also performed during the t RAS,MIN - tRCD,MIN interval (if more than about four column operations are performed, this interval must be increased). The precharge operation requires the interval tRP,MIN to complete. Adjacent Banks: An RDRAM with an "s" designation (256Kx32sx16) indicates it contains "split banks". This means the sense amps are shared between two adjacent banks. The only exception is that sense amp 0 and sense amp 0, 15, 16, and 31are not shared. When a row in a bank is activated, the two adjacent sense amps are connected to (associated with) that bank and are not available for use by the two adjacent banks. These two adjacent banks must remain precharged while the selected bank goes through its activate, restore, read/write, and precharge operations. For example (referring to the block diagram of Figure 2), if bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will both be loaded with one of the 512 rows (with 512 bytes loaded into each sense amp from the 1Kbyte row - 256 bytes to the DQA side and 256 bytes to the DQB side). While this row from bank 5 is being accessed, no rows may be accessed in banks 4 or 6 because of the sense amp sharing. Page 17 Rev. 0.9 July 1999 KM416RD8AS Precharge Mechanisms Figure 13 shows an example of precharge with the ROWR packet mechanism. The PRER command must occur a time Target Direct RDRAMTM tRAS after the ACT command, and a time tRP before the next ACT command. This timing will serve as a baseline aginst which the other precharge mechanisms can be compared. a0 = {Da,Ba,Ra} a5 = {Da,Ba} b0 = {Da,Ba,Rb} T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 tRAS DQA7..0 DQB7..0 tRC Figure 13: Precharge via PRER Command in ROWR Packet Figure 14 (top) shows an example of precharge with a RDA command. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these commands is a RDA, which causes the bank to automatically precharge when the final read has finished. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLC packet with the RDA command. The RDA command should be treated as a RD command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Figure 14 (middle) shows an example of precharge with a WRA command. As in the RDA example, a bank is activated with an ROWA packet on the ROW pins. Then, two dualocts are written with WR commands in COLC packets on the COL pins. The second of these commands is a WRA, which causes the bank to automatically precharge when the final write has been retired. The timing of this automatic precharge is equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time tOFFP from the COLC packet that causes the automatic retire. The WRA command should be treated as a WR command in a COLC packet as well as a simultaneous (but offset) PRER command in an ROWR packet when analyzing interactions with other packets. Note that the automatic retire is triggered by a COLC packet a time tRTR after the COLC packet with the WR command unless the second COLC contains a RD command to the same device. This is described in more detail in Figure 17. Figure 14 (bottom) shows an example of precharge with a PREX command in an COLX packet. A bank is activated with an ROWA packet on the ROW pins. Then, a series of four dualocts are read with RD commands in COLC packets on the COL pins. The fourth of these COLC packets includes an COLX packet with a PREX command. This causes the bank to precharge with timing equivalent to a PRER command in an ROWR packet on the ROW pins that is offset a time t OFFP from the COLX packet with the PREX command. tRP ACT a0 PRER a5 ACT b0 Page 18 Rev. 0.9 July. 1999 KM416RD8AS Target Direct RDRAMTM COLC Packet: RDA Precharge Offset T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM The RDA precharge is equivalent to a PRER command here ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 PRER a5 ACT b0 tOFFP RD a1 RD a2 RD a3 RDA a4 Q (a1) Q (a2) Q (a3) Q (a4) Transaction a: RD a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba,Ca3} a2 = {Da,Ba,Ca2} a4 = {Da,Ba,Ca4} a5 = {Da,Ba} COLC Packet: WDA Precharge Offset T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 PRER a5 ACT b0 tRTR WR a1 WRA a2 retire (a1) retire (a2) MSK (a1) MSK (a2) tOFFP D (a1) D (a2) Transaction a: WR a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a5 = {Da,Ba} COLX Packet: PREX Precharge Offset T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM The PREX precharge command is equivalent to a PRER command here ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 PRER a5 ACT b0 tOFFP RD a1 RD a2 RD a3 RD a4 PREX a5 Q (a1) Q (a2) Q (a3) Q (a4) Transaction a: RD a0 = {Da,Ba,Ra} a1 = {Da,Ba,Ca1} a3 = {Da,Ba,Ca3} a2 = {Da,Ba,Ca2} a4 = {Da,Ba,Ca4} a5 = {Da,Ba} Figure 14: Offsets for Alternate Precharge Mechanisms Page 19 Rev. 0.9 July 1999 KM416RD8AS Read Transaction - Example Figure 15 shows an example of a read transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time tRCD later a RD a1 command is issued in a COLC packet. Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the RD command includes device, bank, and column address (abbreviated as a1). A time tCAC after the RD command the read data dualoct Q(a1) is returned by the device. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time tCC after the first COLC packet on the COL pins a second is issued. It contains a RD a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time tCAC after the second RD command a second read data dualoct Q(a2) is returned by the device. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address Target Direct RDRAMTM includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time t RAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the t RAS interval). The PRER command must also occur a time t RDP or more after the last RD command. Note that the t RDP value shown is greater than the tRDP,MIN specification in Table 22. This transaction example reads two dualocts, but there is actually enough time to read three dualocts before t RDP becomes the limiting parameter rather than t RAS. If four dualocts were read, the packet with PRER would need to shift right (be delayed) by one tCYCLE (note - this case is not shown). Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time tRC or more after the first ACT command and a time tRP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRC ROW2 ..ROW0 COL4 ..COL0 tRCD DQA7..0 DQB7..0 tCAC Transaction a: RD Transaction b: xx a0 = {Da,Ba,Ra} b0 = {Da,Ba,Rb} ACT a0 PRER a3 ACT b0 tRAS RD a1 RD a2 tRP tCC tRDP Q (a1) Q (a2) tCAC a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba} Figure 15: Read Transaction Example Page 20 Rev. 0.9 July. 1999 KM416RD8AS Write Transaction - Example Figure 16 shows an example of a write transaction. It begins by activating a bank with an ACT a0 command in an ROWA packet. A time tRCD-tRTR later a WR a1 command is issued in a COLC packet (note that the tRCD interval is measured to the end of the COLC packet with the first retire command). Note that the ACT command includes the device, bank, and row address (abbreviated as a0) while the WR command includes device, bank, and column address (abbreviated as a1). A time tCWD after the WR command the write data dualoct D(a1) is issued. Note that the packets on the ROW and COL pins use the end of the packet as a timing reference point, while the packets on the DQA/DQB pins use the beginning of the packet as a timing reference point. A time tCC after the first COLC packet on the COL pins a second COLC packet is issued. It contains a WR a2 command. The a2 address has the same device and bank address as the a1 address (and a0 address), but a different column address. A time tCWD after the second WR command a second write data dualoct D(a2) is issued. A time tRTR after each WR command an optional COLM packet MSK (a1) is issued, and at the same time a COLC packet is issued causing the write buffer to automatically retire. See Figure 17 for more detail on the write/retire mechanism. If a COLM packet is not used, all data bytes are unconditionally written. If the COLC packet which causes Target Direct RDRAMTM the write buffer to retire is delayed, then the COLM packet (if used) must also be delayed. Next, a PRER a3 command is issued in an ROWR packet on the ROW pins. This causes the bank to precharge so that a different row may be activated in a subsequent transaction or so that an adjacent bank may be activated. The a3 address includes the same device and bank address as the a0, a1, and a2 addresses. The PRER command must occur a time t RAS or more after the original ACT command (the activation operation in any DRAM is destructive, and the contents of the selected row must be restored from the two associated sense amps of the bank during the tRAS interval). A PRER a3 command is issued in an ROWR packet on the ROW pins. The PRER command must occur a time t RTP or more after the last COLC which causes an automatic retire. Finally, an ACT b0 command is issued in an ROWR packet on the ROW pins. The second ACT command must occur a time tRC or more after the first ACT command and a time t RP or more after the PRER command. This ensures that the bank and its associated sense amps are precharged. This example assumes that the second transaction has the same device and bank address as the first transaction, but a different row address. Transaction b may not be started until transaction a has finished. However, transactions to other banks or other devices may be issued during transaction a. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRC ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 PRER a3 ACT b0 tRCD tRAS WR a1 WR a2 retire (a1) retire (a2) MSK (a1) MSK (a2) tRP tRTP tRTR tCC tCWD Transaction a: WR Transaction b: xx a0 = {Da,Ba,Ra} b0 = {Da,Ba,Rb} tRTR D (a1) D (a2) tCWD a1 = {Da,Ba,Ca1} a2 = {Da,Ba,Ca2} a3 = {Da,Ba} Figure 16: Write Transaction Example Page 21 Rev. 0.9 July 1999 KM416RD8AS Write/Retire - Examples The process of writing a dualoct into a sense amp of an RDRAM bank occurs in two steps. The first step consists of transporting the write command, write address, and write data into the write buffer. The second step happens when the RDRAM automatically retires the write buffer (with an optional bytemask) into the sense amp. This two-step write process reduces the natural turn-around delay due to the internal bidirectional data pins. Figure 17 (left) shows an example of this two step process. The first COLC packet contains the WR command and an address specifying device, bank and column. The write data dualoct follows a time tCWD later. This information is loaded into the write buffer of the specified device. The COLC Target Direct RDRAMTM packet which follows a time t RTR later will retire the write buffer. The retire will happen automatically unless (1) a COLC packet is not framed (no COLC packet is present and the S bit is zero), or (2) the COLC packet contains a RD command to the same device. If the retire does not take place at time tRTR after the original WR command, then the device continues to frame COLC packets, looking for the first that is not a RD directed to itself. A bytemask MSK(a1) may be supplied in a COLM packet aligned with the COLC that retires the write buffer at time t RTR after the WR command. The memory controller must be aware of this two-step write/retire process. Controller performance can be improved, but only if the controller design accounts for several side effects. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T 1 T 2 T 3 T4 T 5 T 6 T 7 T8 T 9 T 10 T 11 T12 T13 T14 T15 T16 T 17 T 18 T 19 T20 T 21 T 22 T 23 0 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 tCWD Transaction a: WR a1= {Da,Ba,Ca1} Retire is automatic here unless: (1) No COLC packet (S=0) or (2) COLC packet is RD to device Da CTM/CFM This RD gets the old data This RD gets the new data ROW2 ..ROW0 tCAC tCAC COL4 ..COL0 DQA7..0 DQB7..0 tCWD Transaction a: WR Transaction b: RD Transaction c: RD WR a1 RD b1 retire (a1) MSK (a1) RD c1 WR a1 retire (a1) MSK (a1) tRTR D (a1) tRTR D (a1) Q (b1) Q (c1) a1= {Da,Ba,Ca1} b1= {Da,Ba,Ca1} c1= {Da,Ba,Ca1} Figure 17: Normal Retire (left) and Retire/Read Ordering (right) Figure 17 (right) shows the first of these side effects. The first COLC packet has a WR command which loads the address and data into the write buffer. The third COLC causes an automatic retire of the write buffer to the sense amp. The second and fourth COLC packets (which bracket the retire packet) contain RD commands with the same device, bank and column address as the original WR command. In other words, the same dualoct address that is written is read both before and after it is actually retired. The first RD returns the old dualoct value from the sense amp before it is overwritten. The second RD returns the new dualoct value that was just written. Figure 18 (left) shows the result of performing a RD command to the same device in the same COLC packet slot that would normally be used for the retire operation. The read may be to any bank and column address; all that matters is that it is to the same device as the WR command. The retire operation and MSK(a1) will be delayed by a time tPACKET as a result. If the RD command used the same bank and column address as the WR command, the old data from the sense amp would be returned. If many RD commands to the same device were issued instead of the single one that is shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to another device or a WR or NOCOP to any device is issued, the retire will take place. Figure 18 (right) illustrates a situation in which the controller wants to issue a WR-WR-RD COLC packet sequence, with all commands addressed to the same device, but addressed to any combination of banks and columns. Page 22 Rev. 0.9 July. 1999 KM416RD8AS Write/Retire Examples - continued The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1) in the write buffer will be overwritten by the second WR dualoct D(b1) if the RD command is issued in the third COLC packet. Target Direct RDRAMTM Therefore, it is required in this situation that the controller issue a NOCOP command in the third COLC packet, delaying the RD command by a time of t PACKET. This situation is explicitly shown in Table 12 for the cases in which tCCDELAY is equal to tRTR. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 tCWD Transaction a: WR Transaction b: RD The retire operation for a write can be held off by a read to the same device CTM/CFM ROW2 ..ROW0 COL4 ..COL0 Q (b1) DQA7..0 The controller must insert a NOCOP to retire (a1) to make room for the data (b1) in the write buffer tCAC WR a1 RD b1 retire (a1) MSK (a1) WR a1 WR b1 retire (a1) MSK (a1) RD c1 tCAC tRTR + tPACKET D (a1) tRTR D (a1) D (b1) DQB7..0 a1= {Da,Ba,Ca1} b1= {Da,Bb,Cb1} tCWD Transaction a: WR Transaction b: WR Transaction c: RD a1= {Da,Ba,Ca1} b1= {Da,Bb,Cb1} c1= {Da,Bc,Cc1} Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right) Figure 19 shows a possible result when a retire is held off for a long time (an extended version of Figure 18-left). After a WR command, a series of six RD commands are issued to the same device (but to any combination of bank and column addresses). In the meantime, the bank Ba to which the WR command was originally directed is precharged, and a different row Rc is activated. When the retire is automatically performed, it is made to this new row, since the write buffer only contains the bank and column address, not the row address. The controller can insure that this doesn't happen by never precharging a bank with an unretired write buffer. Note that in a system with more than one RDRAM, there will never be more than two RDRAMs with unretired write buffers. This is because a WR command issued to one device automatically retires the write buffers of all other devices written a time t RTR before or earlier. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRC ROW2 ..ROW0 COL4 ..COL0 tRCD DQA7..0 DQB7..0 tCWD Transaction a: WR Transaction b: RD Transaction c: WR a0 = {Da,Ba,Ra} b1 = {Da,Bb,Cb1} b4 = {Da,Bb,Cb4} c0 = {Da,Ba,Rc} ACT a0 PRER a2 ACT c0 The retire operation puts the write data in the new row tRAS WR a1 RD b1 RD b2 RD b3 tRP RD b4 RD b5 RD b6 retire (a1) MSK (a1) tRTR D (a1) Q (b1) Q (b2) Q (b3) Q (b4) Q (b5) tCAC a1 = {Da,Ba,Ca1} b2 = {Da,Bb,Cb2} b5 = {Da,Bb,Cb5} a2 = {Da,Ba} b3= {Da,Bb,Cb3} b6 = {Da,Bb,Cb6} WARNING This sequence is hazardous and must be used with caution Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row Page 23 Rev. 0.9 July 1999 KM416RD8AS Interleaved Write - Example Figure 20 shows an example of an interleaved write transaction. Transactions similar to the one presented in Figure 16 are directed to non-adjacent banks of a single RDRAM. This allows a new transaction to be issued once every tRR interval rather than once every tRC interval (four times more often). The DQ data pin efficiency is 100% with this sequence. With two dualocts of data written per transaction, the COL, DQA, and DQB pins are fully utilized. Banks are precharged Target Direct RDRAMTM using the WRA autoprecharge option rather than the PRER command in an ROWR packet on the ROW pins. In this example, the first transaction is directed to device Da and bank Ba. The next three transactions are directed to the same device Da, but need to use different, non-adjacent banks Bb, Bc, Bd so there is no bank conflict. The fifth transaction could be redirected back to bank Ba without interference, since the first transaction would have completed by then (t RC has elapsed). Each transaction may use any value of row address (Ra, Rb, ..) and column address (Ca1, Ca2, Cb1, Cb2, ...). T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRC ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 ACT b0 ACT c0 ACT d0 ACT e0 Transaction e can use the same bank as transaction a ACT f0 tRCD WR z1 WRA z2 MSK (y1) MSK (y2) WR a1 MSK (z1) tRR WRA a2 WR b1 WRA b2 WR c1 WRA c2 WR d1 MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2) MSK (c1) WR d2 WR e1 WR e2 MSK (c2) MSK (d1) MSK (d2) tCWD D (x2) D (y1) D (y2) D (z1) D (z2) D (a1) D (a2) D (b1) D (b2) D(c1) D (c2) D (d1) Q (d1) Transaction y: WR Transaction z: WR Transaction a: WR Transaction b: WR Transaction c: WR Transaction d: WR Transaction e: WR Transaction f: WR y0 = {Da,Ba+4,Ry} z0 = {Da,Ba+6,Rz} a0 = {Da,Ba,Ra} b0 = {Da,Ba+2,Rb} c0 = {Da,Ba+4,Rc} d0 = {Da,Ba+6,Rd} e0 = {Da,Ba,Re} f0 = {Da,Ba+2,Rf} y1 = {Da,Ba+4,Cy1} z1 = {Da,Ba+6,Cz1} a1 = {Da,Ba,Ca1} b1 = {Da,Ba+2,Cb1} c1 = {Da,Ba+4,Cc1} d1 = {Da,Ba+6,Cd1} e1 = {Da,Ba,Ce1} f1 = {Da,Ba+2,Cf1} y2= {Da,Ba+4,Cy2} z2= {Da,Ba+6,Cz2} a2= {Da,Ba,Ca2} b2= {Da,Ba+2,Cb2} c2= {Da,Ba+4,Cc2} d2= {Da,Ba+6,Cd2} e2= {Da,Ba,Ce2} f2= {Da,Ba+2,Cf2} y3 = {Da,Ba+4} z3 = {Da,Ba+6} a3 = {Da,Ba} b3 = {Da,Ba+2} c3 = {Da,Ba+4} d3 = {Da,Ba+6} e3 = {Da,Ba} f3 = {Da,Ba+2} Figure 20: Interleaved Write Transaction with Two Dualoct Data Length Interleaved Read - Example Figure 21 shows an example of interleaved read transactions. Transactions similar to the one presented in Figure 15 are directed to non-adjacent banks of a single RDRAM. The address sequence is identical to the one used in the previous write example. The DQ data pins efficiency is also 100%. The only difference with the write example (aside from the use of the RD command rather than the WR command) is the use of the PREX command in a COLX packet to precharge the banks rather than the RDA command. This is done because the PREX is available for a readtransaction but is not available for a masked write transaction. that bubble cycles need to be inserted by the controller at read/write boundaries. The DQ data pin efficiency for the example in Figure 22 is 32/42 or 76%. If there were more RDRAMs on the Channel, the DQ pin efficiency would approach 32/34 or 94% for the two-dualoct RRWW sequence (this case is not shown). In Figure 22, the first bubble type tCBUB1 is inserted by the controller between a RD and WR command on the COL pins. This bubble accounts for the round-trip propagation delay that is seen by read data, and is explained in detail in Figure 4. This bubble appears on the DQA and DQB pins as tDBUB1 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as t RBUB1. Interleaved RRWW - Example Figure 22 shows a steady-state sequence of 2-dualoct RD/RD/WR/WR.. transactions directed to non-adjacent banks of a single RDRAM. This is similar to the interleaved write and read examples in Figure 20 and Figure 21 except Page 24 Rev. 0.9 July. 1999 KM416RD8AS Target Direct RDRAMTM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRC ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 ACT b0 ACT c0 ACT d0 ACT e0 Transaction e can use the same bank as transaction a ACT f0 tRCD RD z1 RD z2 PREX y3 RD a1 RD a2 PREX z3 RD b1 RD b2 PREX a3 RD c1 tRR RD c2 PREX b3 RD d1 RDd2 PREX c3 RD e1 RD e2 PREX d3 tCAC Q (x2) Q (y1) Q (y2) Q (z1) Q (z2) Q (a1) Q (a2) Q (b1) Q (b2) Q (c1) Q (c2) Q (d1) Transaction y: RD Transaction z: RD Transaction a: RD Transaction b: RD Transaction c: RD Transaction d: RD Transaction e: RD Transaction f: RD y0 = {Da,Ba+4,Ry} z0 = {Da,Ba+6,Rz} a0 = {Da,Ba,Ra} b0 = {Da,Ba+2,Rb} c0 = {Da,Ba+4,Rc} d0 = {Da,Ba+6,Rd} e0 = {Da,Ba,Re} f0 = {Da,Ba+2,Rf} y1 = {Da,Ba+4,Cy1} z1 = {Da,Ba+6,Cz1} a1 = {Da,Ba,Ca1} b1 = {Da,Ba+2,Cb1} c1 = {Da,Ba+4,Cc1} d1 = {Da,Ba+6,Cd1} e1 = {Da,Ba,Ce1} f1 = {Da,Ba+2,Cf1} y2= {Da,Ba+4,Cy2} z2= {Da,Ba+6,Cz2} a2= {Da,Ba,Ca2} b2= {Da,Ba+2,Cb2} c2= {Da,Ba+4,Cc2} d2= {Da,Ba+6,Cd2} e2= {Da,Ba,Ce2} f2= {Da,Ba+2,Cf2} y3 = {Da,Ba+4} z3 = {Da,Ba+6} a3 = {Da,Ba} b3 = {Da,Ba+2} c3 = {Da,Ba+4} d3 = {Da,Ba+6} e3 = {Da,Ba} f3 = {Da,Ba+2} Figure 21: Interleaved Read Transaction with Two Dualoct Data Length The second bubble type tCBUB2 is inserted (as a NOCOP command) by the controller between a WR and RD command on the COL pins when there is a WR-WR-RD sequence to the same device. This bubble enables write data to be retired from the write buffer without being lost, and is explained in detail in Figure 18. There would be no bubble if address c0 and address d0 were directed to different devices. This bubble appears on the DQA and DQB pins as t DBUB2 between a write data dualoct D and read data dualoct Q. This bubble also appears on the ROW pins as t RBUB2. T0 T 1 T 2 T 3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T 17 T 18 T 19 T20 T 21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T 33 T 34 T 35 T36 T 37 T 38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRBUB1 ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 ACT a0 ACT b0 ACT c0 tRBUB2 Transaction e can use the same bank as transaction a ACT d0 ACT e0 tCBUB2 RD z1 RD z2 RD a1 RD a2 PREX z3 tCBUB1 WR b1 MSK (y2) WRA b2 PREX a3 tCBUB2 WR c1 WRA c2 NOCOP MSK (b1) MSK (b2) MSK (c1) NOCOP MSK (c2) RDd0 RDf1 tDBUB1 D (y2) tDBUB2 Q (z1) Q (z2) Q (a1) Q (a2) D (b1) D (b2) D (c1) tDBUB1 D (c2) Transaction y: WR Transaction z: RD Transaction a: RD Transaction b: WR Transaction c: WR Transaction d: RD Transaction e: RD Transaction f: WR y0 = {Da,Ba+4,Ry} z0 = {Da,Ba+6,Rz} a0 = {Da,Ba,Ra} b0 = {Da,Ba+2,Rb} c0 = {Da,Ba+4,Rc} d0 = {Da,Ba+6,Rd} e0 = {Da,Ba,Re} f0 = {Da,Ba+2,Rf} y1 = {Da,Ba+4,Cy1} z1 = {Da,Ba+6,Cz1} a1 = {Da,Ba,Ca1} b1 = {Da,Ba+2,Cb1} c1 = {Da,Ba+4,Cc1} d1 = {Da,Ba+6,Cd1} e1 = {Da,Ba,Ce1} f1 = {Da,Ba+2,Cf1} y2= {Da,Ba+4,Cy2} z2= {Da,Ba+6,Cz2} a2= {Da,Ba,Ca2} b2= {Da,Ba+2,Cb2} c2= {Da,Ba+4,Cc2} d2= {Da,Ba+6,Cd2} e2= {Da,Ba,Ce2} f2= {Da,Ba+2,Cf2} y3 = {Da,Ba+4} z3 = {Da,Ba+6} a3 = {Da,Ba} b3 = {Da,Ba+2} c3 = {Da,Ba+4} d3 = {Da,Ba+6} e3 = {Da,Ba} f3 = {Da,Ba+2} Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length Page 25 Rev. 0.9 July 1999 KM416RD8AS Control Register Transactions The RDRAM has two CMOS input pins SCK and CMD and two CMOS input/output pins SIO0 and SIO1. These provide serial access to a set of control registers in the RDRAM. These control registers provide configuration information to the controller during the initialization process. They also allow an application to select the appropriate operating mode of the RDRAM. SCK T4 T20 T36 Target Direct RDRAMTM SCK (serial clock) and CMD (command) are driven by the controller to all RDRAMs in parallel. SIO0 and SIO1 are connected (in a daisy chain fashion) from one RDRAM to the next. In normal operation, the data on SIO0 is repeated on SIO1, which connects to SIO0 of the next RDRAM (the data is repeated from SIO1 to SIO0 for a read data packet). The controller connects to SIO0 of the first RDRAM. T52 T68 1 0 CMD 1111 0000 next transaction 1 00000000...00000000 00000000...00000000 00000000...00000000 00000000...00000000 1111 0 SIO0 SRQ - SWR command SA SD SINT 1 Each packet is repeated from SIO0 to SIO1 SRQ - SWR command SA SD SINT 0 1 0 SIO1 Figure 23: Serial Write (SWR) Transaction to Control Register Write and read transactions are each composed of four packets, as shown in Figure 23 and Figure 24. Each packet consists of 16 bits, as summarized in Table 16 and Table 17. The packet bits are sampled on the falling edge of SCK. A transaction begins with a SRQ (Serial Request) packet. This packet is framed with a 11110000 pattern on the CMD input (note that the CMD bits are sampled on both the falling edge and the rising edge of SCK). The SRQ packet contains the SOP3..SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5..SDEV0 (Serial Device address) selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is set, then all RDRAMs are selected. The SA (Serial Address) SCK T4 T20 T36 packet contains a 12 bit address for selecting a control register. A write transaction has a SD (Serial Data) packet next. This contains 16 bits of data that is written into the selected control register. A SINT (Serial Interval) packet is last, providing some delay for any side-effects to take place. A read transaction has a SINT packet, then a SD packet. This provides delay for the selected RDRAM to access the control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet types. The SCK cycle time will accomodate the total delay. T52 T68 1 0 next transaction 1 CMD 1111 0000 00000000...00000000 00000000...00000000 00000000...00000000 addressed RDRAM drives 0/SD15..SD0/0 on SIO0 00000000...00000000 controller drives 0 on SIO0 1111 0 1 0 0 1 0 0 SIO0 SRQ - SRD command SA SINT 0 SD non-addressed RDRAMs pass 0/SD15..SD0/0 from SIO1 to SIO0 SIO1 First 3 packets are repeated from SIO0 to SIO1 SRQ - SRD command SA SINT 0 SD Figure 24: Serial Read (SRD) Transaction Control Register Page 26 Rev. 0.9 July. 1999 KM416RD8AS Control Register Packets Table 14 summarizes the formats of the four packet types for control register transactions. Table 15 summarizes the fields that are used within the packets. Figure 25 shows the transaction format for the SETR, CLRR, and SETF commands. These transactions consist of a single SRQ packet, rather than four packets like the SWR and SRD commands. The same framing sequence on the CMD input is used, however. These commands are used during initialization prior to any control register read or write transactions. SCK T4 Target Direct RDRAMTM T20 1 0 1 CMD 1111 0000 00000000...00000000 0 1 SIO0 SRQ packet - SETR/CLRR/SETF The packet is repeated from SIO0 to SIO1 0 1 0 SIO1 SRQ packet - SETR/CLRR/SETF Figure 25: SETR, CLRR,SETF Transaction Table 14: Control Register Packet Formats SCK Cycle 0 1 2 3 4 5 6 7 SIO0 or SIO1 for SRQ rsrv rsrv rsrv rsrv rsrv SDEV5 SOP3 SOP2 SIO0 or SIO1 for SA rsrv rsrv rsrv rsrv SA11 SA10 SA9 SA8 SIO0 or SIO1 for SINT 0 0 0 0 0 0 0 0 SIO0 or SIO1 for SD SD15 SD14 SD13 SD12 SD11 SD10 SD9 SD8 SCK Cycle 8 9 10 11 12 13 14 15 SIO0 or SIO1 for SRQ SOP1 SOP0 SBC SDEV4 SDEV3 SDEV2 SDEV1 SDEV0 SIO0 or SIO1 for SA SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SIO0 or SIO1 for SINT 0 0 0 0 0 0 0 0 SIO0 or SIO1 for SD SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 Table 15: Field Description for Control Register Packets Field rsrv SOP3..SOP0 Description Reserved. Should be driven as "0" by controller. 0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}. 0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}. 0010 - SETR. Set Reset bit, all control registers assume their reset values.a 16 tSCYCLE delay until CLRR command. 0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command. 1011 - CLRR. Clear Reset bit, all control registers retain their reset values.a 4 tSCYCLE delay until next command. 1111 - NOP. No serial operation. 0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings. SDEV5..SDEV0 SBC SA11..SA0 SD15..SD0 Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to which the transaction is directed. Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection. Serial address. Selects which control register of the selected RDRAM is read or written. Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM. a. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called "SETR/CLRR Reset". Page 27 Rev. 0.9 July 1999 KM416RD8AS Initialization T0 SCK 0 1 CMD 1100 Target Direct RDRAMTM At this point, Algorithm InitDev is complete and all RDRAMs have a unique device address SDEVID5..0 for control register transactions. Note that the SDEVID address value of an RDRAM indicates its position in the daisychained CMOS serial pins. This will not necessarily be the same value as the DEVID register which is used for memory transactions. The next steps taken by the controller will vary depending upon the application, so only a rough outline can be given here. ======================================= Algorithm InitDev: Assign SDEVID Device Addresses 1. 2. Issue SIO Reset sequence (see Figure 26). Issue one SETR transaction: * SOP3..SOP0 = 0010 (SETR command) * SBC = 1 (Broadcast) * SDEV5..SDEV0 = 000000 (don't care). Wait 16 SCK cycles. Issue one CLRR transaction: * SOP3..SOP0 = 0011 (CLRR command) * SBC = 1 (Broadcast) * SDEV5..SDEV0 = 000000 (don't care). Wait 4 SCK cycles. Issue one SETF transaction: * SOP3..SOP0 = 0100 (SETF command) * SBC = 1 (Broadcast) * SDEV5..SDEV0 = 000000 (don't care). Wait 4 SCK cycles. Issue one register write transaction: * SOP3..SOP0 = 0001 (SWR command) * SBC = 1 (broadcast) * SDEV5..SDEV0 = 000000 (don't care). * SA11..SA0 = 021 16 (INIT control register). * SD15..SD0 = 401f 16 (SRP<=0, SDEVID<=3f). Set INDX5..INDX0 to 00000002. INDX is a counter in the Controller which acts as a loop index. Issue one register write transaction (SRP<=1, SDEVID<=INDX): * SOP3..SOP0 = 0001 (SWR command) * SBC = 0 (non-broadcast) *SDEV5..SDEV0 = 111111. * SA11..SA0 = 021 16 (INIT control register). * SD15..SD0 = {0 2, INDX5, 000001002, INDX4..INDX0}. Increment INDX5..INDX0. Repeat Steps (8) and (9) an additional (N-1) times. tPAUSE delay, then tPDNXA+ tPDNXB delay (to allow DLLs to lock), then access all banks twice from a precharged state; i.e perform one of the two following two (broadcast) sequences to each bank of all RDRAMs: a. REFA/REFP, REFA/REFP, REFA/REFP or a. REFP, REFA/REFP, REFA/REFP T16 1 00000000...00000000 0 1 SIO0 0000000000000000 The packet is repeated from SIO0 to SIO1 0 1 0 SIO1 0000000000000000 Figure 26: SIO Reset Sequence Initialization refers to the process that a controller must go through after power is applied to the system or the system is reset. The controller prepares the RDRAM sub-system for normal Channel operation by using a sequence of control register transactions on the serial CMOS pins. The first step in this sequence is to assign unique serial device addresses to all the RDRAMs. This is done with Algorithm InitDev, shown in the opposite column. The controller assumes that there are no more that "N" RDRAMs on the Channel (the Channel maximum is 32, but some applications may have a lower limit). First, the SIO0 and SIO1 pin directionality is established with the sequence in step 1. The controller then resets all RDRAMs, using broadcast SETR and CLRR commands (steps 2,3,4,5) with a delay in between (this is also called SIO Reset). In step 6, a SETF command establishs the normal clock frequency. See Figure 25 for the format of SETR, CLRR, and SETF transactions. In step 7 the SIO0-toSIO1 link is broken in all RDRAMs, so the controller is only talking to the first RDRAM. Also, the SDEVID field is set to its maximum value. Next, the loop index INDX is initialized (step 8). In step 9, the SDEVID field is loaded with the INDX value, and the SRP bit is set so the next RDRAM becomes accessible. In step 10, the INDX value is incremented, and in step 11, steps 8 and 9 are repeated for the remaining RDRAMs. Finally, it will be necessary for the controller to force a 200s pause interval to allow the RDRAM core timing circuits to stabilize. All banks of all RDRAMs must also be accessed twice. An access is an activate (ACT) and a precharge (PRE) command. This may be accomplished with the refresh commands. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Page 28 Rev. 0.9 July 1999 KM416RD8AS Initialization (continued) In essence, the controller must read all the read-only configuration registers of all RDRAMs, it must process this information, and then it must write all the read-write registers to place the RDRAMs into the proper operating mode. The most important of these read-write registers are DEVID (the device address for memory transactions) and TRDLY (which sets the delay value for memory read data). During the initialization process, it is necessary for the controller to perform 128 current control operations (3xCAL, 1xCAL/SAM) and one temperature calibrate operation (TCEN/TCAL) after reset or after powerdown (PDN) exit. There are two classes of 128Mbit RDRAM. They are distinguished by the "S28IECO" bit in the SPD. The behavior of the RDRAM at initialization is slightly different for the two types: S28IECO=0: Upon powerup the device enters ATTN state. The serial operations SETR, CLRR, and SETF are performed without requiring a SDEVID match of the SBC bit (broadcast) to be set. S28IECO=1: Upon powerup the device enters PDN state. The serial operations SETR, CLRR, and SETF require a SDEVID match. See the document detailing the reference initialization procedure for more information on how to handle this in a system. After the step of equalizing the total read delay of each RDRAM has been completed (i.e. after the TCDLY0 and TCDLY1 fields have been written for the final time), a single final memory read transaction should be made to each RDRAM in order to ensure that the output pipeline stages have been cleared. Target Direct RDRAMTM Page 29 Rev. 0.9 July 1999 KM416RD8AS Control Register Summary Table 16 summarizes the RDRAM control registers. Detail is provided for each control register in Figure 27 through Figure 43. Read-only bits which are shaded gray are unused and return zero. Read-write bits which are shaded gray are reserved and should always be written with zero. The RIMM Target Direct RDRAMTM SPD Application Note describes additional read-only configuration registers which are present on Direct RIMMs. The state of the register fields are potentially affected by the IO Reset operation or the SETR/CLRR operation. This is indicated in the text accompanying each register diagram. Table 16: Control Register Summary SA11..SA0 02116 Register INIT Field SDEVID PSX SRP NSR PSR LSR TEN TSQ DIS 02216 02316 TEST34 CNFGA TEST34 REFBIT DBL MVER PVER 02416 CNFGB BYT DEVTYP SPT CORG SVER 04016 04116 04216 04316 DEVID REFB REFR CCA DEVID REFB REFR CCA ASYMA 04416 CCB CCB ASYMB 04516 NAPX NAPXA NAPX DQS 04616 04716 04816 PDNXA PDNX TPARM PDNXA PDNX TCAS TCLS TCDLY0 read-write/ read-only read-write, 6 bits read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 1 bit read-write, 16 bits read-only, 3 bit read-only, 1 bit read-only, 6 bit read-only, 6 bit read-only, 1 bit read-only, 3 bit read-only, 1 bit read-only, 6 bit read-only, 6 bit read-write, 5 bits read-write, 4 bits read-write, 9 bits read-write, 7 bits read-write, 2 bits read-write, 7 bits read-write, 2 bits read-write, 5 bits read-write, 5 bits read-write, 1 bits read-write, 13 bits read-write, 13 bits read-write, 2 bits read-write, 2 bits read-write, 3 bits Description Serial device ID. Device address for control register read/write. Power select exit. PDN/NAP exit with device addr on DQA5..0. SIO repeater. Used to initialize RDRAM. NAP self-refresh. Enables self-refresh in NAP mode. PDN self-refresh. Enables self-refresh in PDN mode. Low power self-refresh. Enables low power self-refresh. Temperature sensing enable. Temperature sensing output. RDRAM disable. Test register. Do not read or write after SIO reset. Refresh bank bits. Used for multi-bank refresh. Double. Specifies doubled-bank architecture Manufacturer version. Manufacturer identification number. Protocol version. Specifies version of Direct protocol supported. Byte. Specifies an 8-bit or 9-bit byte size. Device type. Device can be RDRAM or some other device category. Split-core. Each core half is an individual dependent core. Core organization. Bank, row, column address field sizes. Stepping version. Mask version number. Device ID. Device address for memory read/write. Refresh bank. Next bank to be refreshed by self-refresh. Refresh row. Next row to be refreshed by REFA, self-refresh. Current control A. Controls IOL output current for DQA. Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA. Current control B. Controls IOL output current for DQB. Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB. NAP exit. Specifies length of NAP exit phase A. NAP exit. Specifies length of NAP exit phase A + phase B. DQ select. Selects CMD framing for NAP/PDN exit. PDN exit. Specifies length of PDN exit phase A. PDN exit. Specifies length of PDN exit phase A + phase B. tCAS-C core parameter. Determines tOFFP datasheet parameter. tCLS-C core parameter. Determines tCAC and tOFFP parameters. tCDLY0-C core parameter. Programmable delay for read data. Page 30 Rev. 0.9 July 1999 KM416RD8AS Table 16: Control Register Summary SA11..SA0 04916 04a16 04b16 Register TFRM TCDLY1 SKIP Field TFRM TCDLY1 AS MSE MS 04c16 04d16 04e16 04f16 08016 - 0ff16 TCYCLE TEST77 TEST78 TEST79 reserved TCYCLE TEST77 TEST78 TEST79 reserved read-write/ read-only read-write, 4 bits read-write, 3 bits read, 1 bit read-write, 1 bit read-write, 1 bit read-write, 14 bits read-write, 16 bits read-write, 16 bits read-write, 16 bits vendor-specific Description Target Direct RDRAMTM tFRM-C core parameter. Determines ROW-COL packet framing interval. tCDLY1-C core parameter. Programmable delay for read data. Auto Skip. Manual Skip Enable. Manual Skip. tCYCLE datasheet parameter. Specifies cycle time in 64ps units. Test register. Write with zero after SIO reset. Test register. Do not read or write after SIO reset. Test register. Do not read or write after SIO reset. Vendor-specific test registers. Do not read or write after SIO reset. Page 31 Rev. 0.9 July 1999 KM416RD8AS . . Target Direct RDRAMTM Control Register: INIT 15 14 13 12 11 10 9 0 8 7 6 5 0 SDE VID DIS TSQ TEN LSR PSR NSR SRP PSX 5 Address: 021 16 4 3 2 1 0 Read/write register. Reset values are undefined except as affected by SIO Reset as noted below. SETR/CLRR Reset does not affect this register. SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0 serial address field of serial request packet for register read/write transactions. This determines which RDRAM is selected for the register read or write operation. SDEVID resets to 3f16. SDEVID4..SDEVID0 PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the DQA5..0 pins. SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. SRP resets to 1. NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can't be set while in NAP mode. NSR resets to 0. PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can't be set while in PDN mode. PSR resets to 0. Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply current is reduced. LSR resets to 0. Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit to be read to determine if a thermal trip point has been exceeded. TEN resets to 0. Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0 when it has not. TSQ is available during a current control operation (see Figure 51). RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits normal operation. This mechanism disables an RDRAM. DIS resets to 0. Figure 27: INIT Register Control Register: CNFGA 15 14 13 12 11 10 9 PVER5..0 = 000001 Address: 023 16 6 5 4 3 2 1 0 DBL REFBIT2..0 1 = 100 Read-only register. REFBIT2..0 - Refresh Bank Bits. Specifies the number of bank address bits used by REFA and REFP commands. Permits multi-bank refresh in future RDRAMs. DBL - Doubled-Bank. DBL=1 means the device uses a doubled-bank architecture with adjacent-bank dependency. DBL=0 means no dependency. MVER5..0 - Manufacturer Version. Specifies the manufacturer identification number. PVER5..0 - Protocol Version. Specifies the Direct Protocol version used by this device: 0 - Compliant with version 0.62 and ECO1-ECO18. 1 - Compliant with version 0.7 and ECO1-ECO38. 2 to 63 - Reserved. 8 7 MVER5..0 = mmmmmm Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the range of the PDNX field (PDNX[2:0] in the PDNX register) may not be large enough to specify the location of the restricted interval in Figure 47. In this case, the effective tS4 parameter must increase and no row or column packets may overlap the restricted interval. See Figure 47 and Table 19. Figure 28: CNFGA Register Page 32 Rev. 0.9 July 1999 KM416RD8AS Control Register: CNFGB 15 14 13 12 11 10 9 SVER5..0 = ssssss Target Direct RDRAMTM Address: 024 16 6 5 4 3 2 1 0 SPT DEVTYP2..0 BYT 1 = 000 B .. Read-only register. BYT - Byte width. B=1 means the device reads and writes 9-bit memory bytes. B=0 means 8 bits. DEVTYP2..0 - Device type. DEVTYP = 000 means that this device is an RDRAM. 8 7 CORG4..0 = xxxxx SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not. CORG4..0 - Core organization. This field specifies the number of bank (3, 4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5, 6, or 7 bits) address bits. The encoding of this field will be specified in a later version of this document. SVER5..0 - Stepping version. Specifies the mask version number of this device. Figure 29: CNFGB Register Control Register: TEST34 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 Address: 02216 4 0 3 0 2 0 1 0 0 0 Control Register: DEVID 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 Address: 04016 4 3 2 1 0 DEVID4..DEVID0 Read/write register. Reset value of TEST34 is zero (from SIO Reset) This register are used for testing purposes. It must not be read or written after SIO Reset. Read/write register. Reset value is undefined. Device Identification register. DEVID4..DEVID0 is compared to DR4..DR0, DC4..DC0, and DX4..DX0 fields for all memory read or write transactions. This determines which RDRAM is selected for the memory read or write transaction. Figure 30: TEST Register Figure 31: DEVID Register Page 33 Rev. 0.9 July 1999 KM416RD8AS Target Direct RDRAMTM Control Register: REFB 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 Address: 04116 4 0 3 2 1 0 Control Register: REFR 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 7 6 5 Address: 04216 4 3 2 1 0 REFB3..REFB0 REFR8..REFR0 Read/write register. Reset value is zero (from SETR/CLRR). Refresh Bank register. REFB3..REFB0 is the bank that will be refreshed next during self-refresh. REFB3..0 is incremented after each self-refresh activate and precharge operation pair. Read/write register. Reset value is zero (from SETR/CLRR). Refresh Row register. REFR8..REFR0 is the row that will be refreshed next by the REFP command or by self-refresh. REFR8..0 is incremented when BR3..0=1111 for the REFA command. REFR8..0 is incremented when REFB3..0=1111 for self-refresh. Figure 32: REFB Register Figure 34: REFR Register Control Register: CCA 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 7 6 5 ASYMA 00 Address: 04316 4 3 2 1 0 Control Register: CCB 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 7 6 5 ASYMB 00 Address: 04416 4 3 2 1 0 CCA6..CCA0 CCB6..CCB0 Read/write register. Reset value is zero (SETR/CLRR or SIO Reset). CCA6..CCA0 - Current Control A. Controls the IOL output current for the DQA7..DQA0 pins. ASYMA0 control the asymmetry of the VOL/VOH voltage swing about the VREF reference voltage for the DQA7..0 pins. Read/write register. Reset value is zero (SETR/CLRR or SIO Reset). CCB6..CCB0 - Current Control B. Controls the IOL output current for the DQB7..DQB0 pins. ASYMB0 control the asymmetry of the VOL/VOH voltage swing about the VREF reference voltage for the DQB7..0 pins. Figure 33: CCA Register Figure 35: CCB Register Page 34 Rev. 0.9 July 1999 KM416RD8AS Control Register: NAPX 15 14 13 12 11 10 9 0 0 0 0 0 DQS Target Direct RDRAMTM Address: 045 16 6 5 4 3 2 1 0 8 7 . Read/write register. Reset value is undefined Note - tSCYCLE is tCYCLE1 (SCK cycle time). NAPXA4..0 - Nap Exit Phase A. This field specifies the number of SCK cycles during the first phase for exiting NAP mode. It must satisfy: NAPXA*t SCYCLE tNAPXA,MAX Do not set this field to zero. NAPX4..0 NAPXA4..0 NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK cycles during the first plus second phases for exiting NAP mode. It must satisfy: NAPX*t SCYCLE NAPXA*t SCYCLE+tNAPXB,MAX Do not set this field to zero. DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5 cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device selection on DQ5..0. See Figure 48 - This field must be written with a 1 for this RDRAM. Figure 36: NAPX Register Control Register: PDNXA 15 14 13 12 11 10 9 0 0 0 8 7 6 5 Address: 04616 4 3 2 1 0 Control Register: PDNX 15 14 13 12 11 10 9 0 0 0 8 7 6 5 Address: 04716 4 3 2 1 0 PDNXA12..0 PDNX12..0 Read/write register. Reset value is undefined PDNXA4..0 - PDN Exit Phase A. This field specifies the number of (64*SCK cycle) units during the first phase for exiting PDN mode. It must satisfy: PDNXA*64*t SCYCLE tPDNXA,MAX Do not set this field to zero. Note - only PDNXA5..0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time). Read/write register. Reset value is undefined PDNX4..0 - PDN Exit Phase A plus B. This field specifies the number of (256*SCK cycle) units during the first plus second phases for exiting PDN mode. It must satisfy: PDNX*256*t SCYCLE PDNXA*64*t SCYCLE+ tPDNXB,MAX Do not set this field to zero. Note - only PDNX2..0 are implemented. Note - tSCYCLE is tCYCLE1 (SCK cycle time). Figure 37: PDNXA Register Figure 38: PDNX Register Page 35 Rev. 0.9 July 1999 KM416RD8AS Control Register: TPARM 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 5 Target Direct RDRAMTM Address: 048 16 4 3 2 1 0 TCDLY0 TCLS TCAS Read/write register. Reset value is undefined. TCAS1..0 - Specifies the tCAS-C core parameter in tCYCLE units. This should be "10" (2*tCYCLE). TCLS1..0 - Specifies the tCLS-C core parameter in tCYCLE units. Should be "10" (2*tCYCLE). TCDLY0 - Specifies the tCDLY0-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all devices to be equalized. This field may be written with the values "010" (2*tCYCLE) through "101" (5*tCYCLE). . The equations relating the core parameters to the datasheet parameters follow: tCAS-C = 2*tCYCLE tCLS-C = 2*tCYCLE tCPS-C = 1*tCYCLE Not programmable tOFFP = tCPS-C + tCAS-C + tCLS-C - 1*tCYCLE = 4*tCYCLE tRCD = tRCD-C + 1*tCYCLE - tCLS-C = tRCD-C - 1*tCYCLE tCAC = 3*tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C (see table below for programming ranges) TCDLY0 tCDLY0-C TCDLY1 000 001 010 010 010 tCDLY1-C 0*tCYCLE 1*tCYCLE 2*tCYCLE 2*tCYCLE 2*tCYCLE tCAC 8*tCYCLE 9*tCYCLE 10*tCYCLE 11*tCYCLE 12*tCYCLE 011 011 011 100 101 3*t CYCLE 3*t CYCLE 3*t CYCLE 4*t CYCLE 5*t CYCLE Figure 39: TPARM Register Control Register: TFRM 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 Address: 04916 4 0 3 2 1 0 Control Register: TCDLY1 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 Address: 04a16 4 0 3 0 2 1 0 TFRM3..0 TCDLY1 Read/write register. Reset value is undefined. TFRM3..0 - Specifies the position of the framing point in tCYCLE units. This value must be greater than or equal to the tFRM,MIN parameter. This is the minimum offset between a ROW packet (which places a device at ATTN) and the first COL packet (directed to that device) which must be framed. This field may be written with the values "0111" (7*tCYCLE) through "1010" (10*tCYCLE). TFRM is usually set to the value which matches the largest tRCD,MIN parameter (modulo 4*tCYCLE) that is present in an RDRAM in the memory system. Thus, if an RDRAM with tRCD,MIN = 11*tCYCLE were present, then TFRM would be programmed to 7*tCYCLE. Read/write register. Reset value is undefined. TCDLY1 - Specifies the value of the tCDLY1-C core parameter in tCYCLE units. This adds a programmable delay to Q (read data) packets, permitting round trip read delay to all devices to be equalized. This field may be written with the values "000" (0*tCYCLE) through "010" (2*tCYCLE). Refer to Figure 39 for more details. Figure 40: TFRM Register Figure 41: TRDLY Register Page 36 Rev. 0.9 July 1999 KM416RD8AS Target Direct RDRAMTM Control Register: SKIP 15 14 13 12 11 10 9 0 0 0 AS MSE MS Address: 04b16 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Control Register: TCYCLE 15 14 13 12 11 10 9 0 0 8 7 6 5 Address: 04c16 4 3 2 1 0 8 0 7 0 0 TCYCLE13..TCYCLE0 Read/write register (except AS field). Reset value is zero (SIO Reset). AS - Autoskip. Read-only value determined by autoskip circuit and stored when SETF serial command is received by RDRAM during initialization. In figure 58, AS=1 corresponds to the early Q(a1) packet and AS=0 to the Q(a1) packet one tCYCLE later for the four uncertain cases. MSE - Manual skip enable (0=auto, 1=manual). MS - Manual skip (MS must be 1 when MSE=1).> During initialization, the RDRAMs at the furthest point in the fifth read domain may have selected the AS=0 value, placing them at the closest point in a sixth read domain. Setting the MSE/MS fields to 1/1 overrides the autoskip value and returns them to the furthest point of the fifth read domain. Figure 42: SKIP Register Read/write register. Reset value is undefined TCYCLE13..0 - Specifies the value of the tCYCLE datasheet parameter in 64ps units. For the tCYCLE,MIN of 2.5ns (2500ps), this field should be written with the value "0002716" (39*64ps). Figure 44: TCYCLE Register Control Register: TEST77 Control Register: TEST78 Control Register: TEST79 15 14 13 12 11 10 9 0 0 0 0 0 0 0 8 0 7 0 6 0 5 0 Address: 04d16 Address: 04e 16 Address: 04f16 4 0 3 0 2 0 1 0 0 0 Read/write registers. Reset value of TEST78,79 is zero ( SIO Reset). Do not read or write TEST78,79 after SIO reset. TEST77 must be written with zero after SIO reset. These registers must only be used for testing purposes. Figure 43: TEST Registers Page 37 Rev. 0.9 July 1999 KM416RD8AS Power State Management Table 17 summarizes the power states available to a Direct RDRAM. In general, the lowest power states have the longest operational latencies. For example, the relative power levels of PDN state and STBY state have a ratio of about 1:110, and the relative access latencies to get read data have a ratio of about 250:1. PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with selfrefresh; an internal timer automatically refreshes all rows of all banks. PDN has a relatively long exit latency because the Target Direct RDRAMTM TCLK/RCLK block must resynchronize itself to the external clock signal. NAP state is another low-power state in which either selfrefresh or REFA-refresh are used to maintain the core. See "Refresh" on page 43 for a description of the two refresh mechanisms. NAP has a shorter exit latency than PDN because the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of NAP entry. This imposes a limit (t NLIMIT) on how long an RDRAM may remain in NAP state before briefly returning to STBY or ATTN to update this synchronization state. Table 17: Power State Summary Power State PDN Description Powerdown state. Blocks consuming power Self-refresh Power State NAP Description Nap state. Similar to PDN except lower wake-up latency. Attention state. Ready for ROW and COL packets. Blocks consuming power Self-refresh or REFA-refresh TCLK/RCLK-Nap REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ demux receiver Core power STBY Standby state. Ready for ROW packets. REFA-refresh TCLK/RCLK ROW demux receiver ATTN ATTNR Attention read state. Ready for ROW and COL packets. Sending Q (read data) packets. REFA-refresh TCLK/RCLK ROW demux receiver COL demux receiver DQ mux transmitter Core power ATTNW Attention write state. Ready for ROW and COL packets. Ready for D (write data) packets. Figure 45 summarizes the transition conditions needed for moving between the various power states. Note that NAP and PDN have been divided into two substates (NAPA/NAP-S and PDN-A/PDN-S) to account for the fact that a NAP or PDN exit may be made to either ATTN or STBY states. At initialization, the SETR/CLRR Reset sequence will put the RDRAM into PDN-S state. The PDN exit sequence involves an optional PDEV specification and bits on the CMD and SIOIN pins. Once the RDRAM is in STBY, it will move to the ATTN/ATTNR/ATTNW states when it receives a nonbroadcast ROWA packet or non-broadcast ROWR packet with the ATTN command. The RDRAM returns to STBY from these three states when it receives a RLX command. Alternatively, it may enter NAP or PDN state from ATTN or STBY states with a NAPR or PDNR command in an ROWR packet. The PDN or NAP exit sequence involves an optional PDEV specification and bits on the CMD and SIO0 pins. The RDRAM returns to the ATTN or STBY state it was originally in when it first entered NAP or PDN. An RDRAM may only remain in NAP state for a time tNLIMIT. It must periodically return to ATTN or STBY. The NAPRC command causes a napdown operation if the RDRAM's NCBIT is set. The NCBIT is not directly visible. It is undefined on reset. It is set by a NAPR command to the RDRAM, and it is cleared by an ACT command to the RDRAM. It permits a controller to manage a set of RDRAMs in a mixture of power states. STBY state is the normal idle state of the RDRAM. In this state all banks and sense amps have usually been left precharged and ROWA and ROWR packets on the ROW pins are being monitored. When a non-broadcast ROWA packet or non-broadcast ROWR packet (with the ATTN command) packet addressed to the RDRAM is seen, the RDRAM enters ATTN state (see the right side of Figure 46). This requires a time tSA during which the RDRAM activates the specified row of the specified bank. A time TFRM*tCYCLE after the ROW packet, the RDRAM will be Page 38 Rev. 0.9 July 1999 KM416RD8AS able to frame COL packets (TFRM is a control register field - see Figure 40). Once in ATTN state, the RDRAM will automatically transition to the ATTNW and ATTNR states as it receives WR and RD commands. automatic Target Direct RDRAMTM provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time t CD after the NAPR command. The RDRAM may be in ATTN or STBY state when the NAPR command is issued. When NAP state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with NAPR, then the RDRAM will return to STBY state when NAP is exited. Figure 47 also shows the PDN entry sequence (right). PDN state is entered by sending a PDNR command in a ROW packet. A time tASP is required to enter PDN state (this specification is provided for power calculation purposes). The clock on CTM/CFM must remain stable for a time t CD after the PDNR command. The RDRAM may be in ATTN or STBY state when the PDNR command is issued. When PDN state is exited, the RDRAM will return to the original starting state (ATTN or STBY). If it is in ATTN state and a RLXR command is specified with PDNR, then the RDRAM will return to STBY state when PDN is exited. The current- and slew-rate-control levels are re-established. The RDRAM's write buffer must be retired with the appropriate COP command before NAP or PDN are entered. Also, all the RDRAM's banks must be precharged before NAP or PDN are entered. The exception to this is if NAP is entered with the NSR bit of the INIT register cleared (disabling selfrefresh in NAP). The commands for relaxing, retiring, and precharging may be given to the RDRAM as late as the ROPa0, COPa0, and XOPa0 packets in Figure 47. No broadcast packets nor packets directed to the RDRAM entering Nap or PDN may overlay the quiet window. This window extends for a time tNPQ after the packet with the NAPR or PDNR command. Figure 48 shows the NAP and PDN exit sequences. These sequences are virtually identical; the minor differences will be highlighted in the following description. Before NAP or PDN exit, the CTM/CFM clock must be stable for a time tCE. Then, on a falling and rising edge of SCK, if there is a "01" on the CMD input, NAP or PDN state will be exited. Also, on the falling SCK edge the SIO0 input must be at a 0 for NAP exit and 1 for PDN exit. If the PSX bit of the INIT register is 0, then a device PDEV5..0 is specified for NAP or PDN exit on the DQA5..0 pins. This value is driven on the rising SCK edge 0.5 or 1.5 SCK cycles after the original falling edge, depending upon the value of the DQS bit of the NAPX register. If the PSX bit of the INIT register is 1, then the RDRAM ignores the ATTNR automatic automatic automatic ATTNW automatic automatic tNLIMIT NAPR * RLXR NAP-A PDEV.CMD* SIO0 NAPR * RLXR PDEV.CMD* SIO0 PDNR * RLXR PDN-A PDEV.CMD*SIO0 PDNR * RLXR ATTN RLX NAP NAP-S PDN PDN-S ATTN NAPR PDNR PDEV.CMD*SIO0 SETR/CLRR STBY Notation: SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets PDNR - PDNR command in ROWR packet NAPR - NAPR command in ROWR packet RLXR - RLX command in ROWR packet RLX - RLX command in ROWR,COLC,COLX packets SIO0 - SIO0 input value PDEV.CMD - (PDEV=DEVID)*(CMD=01) ATTN - ROWA packet (non-broadcast) or ROWR packet (non-broadcast) with ATTN command Figure 45: Power State Transition Diagram Once the RDRAM is in ATTN, ATTNW, or ATTNR states, it will remain there until it is explicitly returned to the STBY state with a RLX command. A RLX command may be given in an ROWR, COLC , or COLX packet (see the left side of Figure 46). It is usually given after all banks of the RDRAM have been precharged; if other banks are still activated, then the RLX command would probably not be given. If a broadcast ROWA packet or ROWR packet (with the ATTN command) is received, the RDRAM's power state doesn't change. If a broadcast ROWR packet with RLXR command is received, the RDRAM goes to STBY. Figure 47 shows the NAP entry sequence (left). NAP state is entered by sending a NAPR command in a ROW packet. A time tASN is required to enter NAP state (this specification is Page 39 Rev. 0.9 July 1999 KM416RD8AS PDEV5..0 address packet and exits NAP or PDN when the wake-up sequence is presented on the CMD wire. The ROW and COL pins must be quiet at a time tS4/tH4 around the indicated falling SCK edge (timed with the PDNX or NAPX register fields). After that, ROW and COL packets may be directed to the RDRAM which is now in ATTN or STBY state. Target Direct RDRAMTM Figure 49 shows the constraints for entering and exiting NAP and PDN states. On the left side, an RDRAM exits NAP state at the end of cycle T 3. This RDRAM may not reenter NAP or PDN state for an interval of t NU0. The RDRAM enters NAP state at the end of cycle T13. This RDRAM may not re-exit NAP state for an interval of t NU1. The equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. NAPX is the value in the NAPX field in the NAPX register. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T 1 T 2 T 3 T4 T 5 T 6 T 7 T8 T 9 T 10 T 11 T12 T13 T14 T15 T16 T 17 T 18 T 19 T20 T 21 T 22 T 23 0 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 tAS Power State ATTN STBY RLXR CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 tSA Power State STBY ATTN ROP a0 COP a1 COP a1 XOP a1 COP a1 XOP a1 COP a1 COP a0 XOP a1 XOP a1 XOP a0 ROP = non-broadcast ROWA or ROWR/ATTN a0 = {d0,b0,r0} a1 = {d1,b1,c1} No COL packets may be placed in the three indicated positions; i.e. at (TFRM - {1,2,3})*t CYCLE. A COL packet to device d0 (or any other device) is okay at (TFRM)*t CYCLE or later. A COL packet to another device (d1!= d0) is okay at (TFRM - 4)*t CYCLE or earlier. RLXC RLXX TFRM*t CYCLE Figure 46: STBY Entry (left) and STBY Exit (right) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T 1 T 2 T 3 T4 T 5 T 6 T 7 T8 T 9 T 10 T 11 T12 T13 T14 T15 T16 T 17 T 18 T 19 T20 T 21 T 22 T 23 0 CTM/CFM tCD ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 tASN Power State a CTM/CFM tCD ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 tASP NAP Power State ATTN/STBYa PDN ATTN/STBYa ROP a0 (PDNR) restricted ROP a0 (NAPR) restricted ROP a1 ROP a1 a0 = {d0,b0,r0,c0} a1 = {d1,b1,r1,c1} No ROW or COL packets directed to device d0 may overlap the restricted interval. No broadcast ROW packets may overlap the quiet interval. ROW or COL packets to a device other than d0 may overlap the restricted interval. ROW or COL packets directed to device d0 after the restricted interval will be ignored. quiet tNPQ quiet tNPQ COP a0 XOP a0 restricted quiet COP a1 XOP a1 COP a0 XOP a0 restricted quiet COP a1 XOP a1 The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry Figure 47: NAP Entry (left) and PDN Entry (right) On the right side of Figure 48, an RDRAM exits PDN state at the end of cycle T3. This RDRAM may not re-enter PDN or NAP state for an interval of tPU0. The RDRAM enters PDN state at the end of cycle T13. This RDRAM may not reexit PDN state for an interval of t PU1. The equations for these two parameters depend upon a number of factors, and are shown at the bottom of the figure. PDNX is the value in the PDNX field in the PDNX register. Page 40 Rev. 0.9 July 1999 KM416RD8AS Target Direct RDRAMTM T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 SCK If PSX=1 in Init register, then NAP/PDN exit is broadcast (no PDEV field). No ROW packets may overlap the restricted interval No COL packets may overlap the restricted interval if device PDEV is exiting the NAP-A or PDN-A states ROP ROP restricted tS4 tH4 COP XOP restricted tS3 tH3 tS3 tH3 PDEV5..0b PDEV5..0b COP XOP tS4 tH4 tCE DQS=0 b,c DQS=1 b CMD 0 1 Effective setup becomes tS4'=t S4+[PDNXA * 64 * t SCYCLE+tPDNXB,MAX]-[PDNX * 256 * t SCYCLE] if [PDNX * 256 * t SCYCLE ] < [PDNXA * 64 * t SCYCLE+tPDNXB,MAX]. SIO0 0/1a The packet is repeated from SIO0 to SIO1 SIO1 Power State a 0/1a (NAPX)*t SCYCLE)/(256*PDNX*t SCYCLE) NAP/PDN DQS=0 b DQS=1b c d Exit STBY/ATTN d The DQS field must be written with "1" for this RDRAM. to STBY or ATTN depends upon whether RLXR was asserted at NAP or PDN entry time Use 0 for NAP exit, 1 for PDN exit b Device selection timing slot is selected by DQS field of NAPX register Figure 48: NAP and PDN Exit T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T0 T 1 T 2 T 3 T4 T 5 T 6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T 17 T 18 T 19 T20 T 21 CTM/CFM NAP entry CTM/CFM PDN entry NAPR ROW2 ..ROW0 SCK NAP exit ROW2 ..ROW0 SCK PDN exit 0 1 PDNR CMD 0 1 CMD 0 1 0 1 tNU0 no entry to NAP or PDN tNU0 = 5*t CYCLE + (2+NAPX)*t SCYCLE tNU1 = 8*t CYCLE - (0.5*t SCYCLE) = 23*t CYCLE if NSR=0 if NSR=1 tNU1 no exit no exit no entry to NAP or PDN tPU0 = 5 * t CYCLE + (2+256 * PDNX) * t SCYCLE tPU1 = 8 * t CYCLE - (0.5 * t SCYCLE) = 23 * t CYCLE if PSR=0 if PSR=1 tPU0 tPU1 Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right) Page 41 Rev. 0.9 July 1999 KM416RD8AS Refresh RDRAMs, like any other DRAM technology, use volatile storage cells which must be periodically refreshed. This is accomplished with the REFA command. Figure 50 shows an example of this. The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the ROWR packet), so that in all devices bank number Ba is activated with row number REFR, where REFR is a control register in the RDRAM. When the command is broadcast and ATTN is set, the power state of the RDRAMs (ATTN or STBY) will remain unchanged. The controller increments the bank address Ba for the next REFA command. When Ba is equal to its maximum value, the RDRAM automatically increments REFR for the next REFA command. On average, these REFA commands are sent once every tREF/2BBIT+RBIT (where BBIT are the number of bank address bits and RBIT are the number of row address bits) so that each row of each bank is refreshed once every tREF interval. The REFA command is equivalent to an ACT command, in terms of the way that it interacts with other packets (see Table 10). In the example, an ACT command is sent after tRR to address b0, a different (non-adjacent) bank than the REFA command. A second ACT command can be sent after a time tRC to address c0, the same bank (or an adjacent bank) as the REFA command. Target Direct RDRAMTM Note that a broadcast REFP command is issued a time tRAS after the initial REFA command in order to precharge the refreshed bank in all RDRAMs. After a bank is given a REFA command, no other core operations (activate or precharge) should be issued to it until it receives a REFP. It is also possible to interleave refresh transactions (not shown). In the figure, the ACT b0 command would be replaced by a REFA b0 command. The b0 address would be broadcast to all devices, and would be {Broadcast, Ba+2, REFR}. Note that the bank address should skip by two to avoid adjacent bank interference. A possible bank incrementing pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14, 0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16, 18, 20, 22, 31}. Every time bank 31 is reached, the REFA command would automatically increment the REFR register. A second refresh mechanism is available for use in PDN and NAP power states. This mechanism is called self-refresh mode. When the PDN power state is entered, or when NAP power state is entered with the NSR control register bit set, then self-refresh is automatically started for the RDRAM. Self-refresh uses an internal time base reference in the RDRAM. This causes an activate and precharge to be carried out once in every tREF/2BBIT+RBIT interval. The REFB and REFR control registers are used to keep track of the bank and row being refreshed. Before a controller places an RDRAM into self-refresh mode, it should perform REFA/REFP refreshes until the bank address is equal to the maximum value. This ensures that no rows are skipped. When a controller returns an RDRAM to REFA/REFP refresh, it should start with the minimum bank address value (zero). T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tRC ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Transaction a: REFA a0 = {Broadcast,Ba,REFR} Transaction b: xx b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb} Transaction c: xx c0 = {Dc, ==Ba, Rc} Transaction d: REFA d0 = {Broadcast,Ba+1,REFR} a1 = {Broadcast,Ba} BBIT = # bank address bits RBIT = # row address bits REFB = REFB3..REFB0 REFR = REFR8..REFR0 REFA a0 ACT b0 REFP a1 ACT c0 REFA d0 tRAS tRR tREF/2BBIT+RBIT tRP Figure 50: REFA/REFP Refresh Transaction Example Page 42 Rev. 0.9 July 1999 KM416RD8AS Current and Temperature Control Figure 51 shows an example of a transaction which performs current control calibration. It is necessary to perform this operation once to every RDRAM in every tCCTRL interval in order to keep the IOL output current in its proper range. This example uses four COLX packets with a CAL command. These cause the RDRAM to drive four calibration packets Q(a0) a time tCAC later. An offset of tRDTOCC must be placed between the Q(a0) packet and read data Q(a1)from the same device. These calibration packets are driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of the INIT register is driven on the DQA5 wire during same interval as the calibration packets. The remaining DQA and DQB wires are not used during these calibration packets. The last COLX packet also contains a SAM command (concatenated with the CAL command). The RDRAM Target Direct RDRAMTM samples the last calibration packet and adjusts its I OL current value. Unlike REF commands, CAL and SAM commands cannot be broadcast. This is because the calibration packets from different devices would interfere. Therefore, a current control transaction must be sent every tCCTRL/N, where N is the number of RDRAMs on the Channel. The device field Da of the address a0 in the CAL/SAM command should be incremented after each transaction. Figure 52 shows an example of a temperature calibration sequence to the RDRAM. This sequence is broadcast once every tTEMP interval to all the RDRAMs on the Channel. The TCEN and TCAL are ROP commands, and cause the slew rate of the output drivers to adjust for temperature drift. During the quiet interval t TCQUIET the devices being calibrated can't be read, but they can be written. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 Read data from the same device from an earlier RD command must be at this packet position or earlier. Read data from a different device from an earlier RD command can be anywhere prior to the Q(a0) packet. . Read data from a different device from a later RD command can be anywhere after to the Q(a0) packet. Read data from the same device from a later RD command must be at this packet position or later. tCCTRL CAL a0 CAL a0 CAL a0 CAL/SAM a0 CAL a2 CAL b0 tCAC Q (a1) Q (a0) tCCSAMTOREAD Q (a1) tREADTOCC Transaction a0: CAL/SAM Transaction a1: RD Transaction a2: CAL/SAM a0 = {Da, Bx} a1 = {Da, Bx} a2 = {Da+1, Bx} DQA5 of the first calibrate packet has the inverted TSQ bit of INIT control register; i.e. logic 0 or high voltage means hot temperature. When used for monitoring, it should be enabled with the DQA3 bit (current control one value) in case there is no RDRAM present: HotTemp = DQA5*DQA3 Figure 51: Current Control CAL/SAM Transaction Example T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T 13 T 14 T 15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T 29 T 30 T 31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T 45 T 46 T 47 CTM/CFM tTEMP ROW2 ..ROW0 COL4 ..COL0 DQA7..0 DQB7..0 TCEN TCAL TCEN tTCEN tTCAL tTCQUIET Any ROW packet may be placed in the gap between the ROW packets with the TCEN and TCAL commands. No read data from devices being calibrated Figure 52: Temperature Calibration (TCEN-TCAL) Transactions to RDRAM Page 43 Rev. 0.9 July 1999 KM416RD8AS Electrical Conditions Table 18: Electrical Conditions Symbol TJ VDD, VDDA VDD,N, VDDA,N vDD,N, vDDA,N VCMOS Target Direct RDRAMTM Parameter and Conditions Junction temperature under bias Supply voltage Supply voltage droop (DC) during NAP interval (tNLIMIT) Supply voltage ripple (AC) during NAP interval (tNLIMIT) Supply voltage for CMOS pins (2.5V controllers) Supply voltage for CMOS pins (1.8V controllers) Min 0 2.50 -2.0 2.50 1.80 2.0 - 0.1 1.6 - 0.12 VREF - 0.5 VREF + 0.3 0.6 -5 1.5 1.6 0.6 0.6 - 0.3 VCMOS/2 + 0.25 Max 90 2.50 + 0.2 2.0 2.0 2.50 + 0.25 1.80 + 0.2 2.0 + 0.1 1.6 + 0.12 VREF - 0.3 VREF + 0.5 1.0 5 2.0 1.9 0.70 0.70 VCMOS/2 - 0.25 VCMOS+0.3 Unit C V % % V V V V V V V % V V V V V V VTERM VREF VDIL VDIH VDIS ADI VX VCM VCIS,CTM VCIS,CFM VIL,CMOS VIH,CMOS Termination voltage Reference voltage RSL data input - low voltage RSL data input - high voltage RSL data input swing: VDIS = VDIH - VDIL RSL data asymmetry: ADI = [(VDIH - VREF) + (VDIL - VREF)]/VDIS RSL clock input - crossing point of true and complement signals RSL clock input - common mode VCM = (VCIH+VCIL)/2 RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins). RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins). CMOS input low voltage CMOS input high voltage Timing Conditions Table 19: Timing Conditions Symbol tCYCLE tCR, tCF tCH, tCL tTR tDCW tDR, tDF tS, tH tDR1, tDF1 tDR2, tDF2 Parameter CTM and CFM cycle times (-800) CTM and CFM input rise and fall times CTM and CFM high and low times CTM-CFM differential (MSE/MS=0/0) Domain crossing window DQA/DQB/ROW/COL input rise/fall times DQA/DQB/ROW/COL-to-CFM setup/hold @ tCYCLE=2.5ns SIO0, SIO1 input rise and fall times CMD, SCK input rise and fall times Min 2.5 0.2 40% 0.0 -0.1 0.2 0.250 Max 2.56 0.5 60% 0.5 0.1 0.65 0.250 5.0 2.0 Unit ns ns tCYCLE tCYCLE tCYCLE ns ns ns ns Figure(s) Figure 53 Figure 53 Figure 53 Figure 42 Figure 59 Figure 54 Figure 54 Figure 56 Figure 56 Page 44 Rev. 0.9July 1999 KM416RD8AS Table 19: Timing Conditions Symbol tCYCLE1 Parameter SCK cycle time - Serial control register transactions SCK cycle time - Power transitions tCH1, tCL1 tS1 tH1 tS2 tH2 tS3 tH3 tS4 tH4 vIL,CMOS vIH,CMOS tNPQ tREADTOCC tCCSAMTOREAD tCE tCD tFRM tNLIMIT tREF tCCTRL tTEMP tTCEN tTCAL tTCQUIET tPAUSE SCK high and low times CMD setup time to SCK rising or falling CMD hold time to SCK rising or falling SIO0 setup time to SCK falling edge SIO0 hold time to SCK falling edge PDEV setup time on DQA5..0 to SCK rising edge. PDEV hold time on DQA5..0 to SCK rising edge. ROW2..0, COL4..0 setup time for quiet window b ROW2..0, COL4..0 hold time for quiet window CMOS input low voltage - over/undershoot voltage duration is less than or equal to 5ns CMOS input high voltage - over/undershoot voltage duration is less than or equal to 5ns Quiet on ROW/COL bits during NAP/PDN entry Offset between read data and CC packets (same device) Offset between CC packet and read data (same device) CTM/CFM stable before NAP/PDN exit CTM/CFM stable after NAP/PDN entry ROW packet to COL packet ATTN framing delay Maximum time in NAP mode Refresh interval Current control interval Temperature control interval TCE command to TCAL command TCAL command to quiet window Quiet window (no read data) RDRAM delay (no RSL operations allowed) 150 2 140 34 tCYCLE edgea Min 1000 10 4.25 1 1 40 35 0 5.5 -1 5 - 0.7 Max - Target Direct RDRAMTM Unit ns ns ns ns ns ns ns ns ns tCYCLE tCYCLE V Figure(s) Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 56 Figure 48, Figure 57 Figure 48 Figure 48 edgec VCMOS/2 0.6 VCMOS + 0.7 10.0 32 100ms 100 2 200.0 VCMOS/2 + 0.6 4 12 8 2 100 7 V tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE s ms ms/tCYCLE ms tCYCLE tCYCLE tCYCLE s Figure 47 Figure 51 Figure 51 Figure 48 Figure 47 Figure 46 Figure 45 Figure 50 Figure 51 Figure 52 Figure 52 Figure 52 Figure 52 page 28 a. With VIL,CMOS =0.5VCMOS-0.6V and VIH,CMOS=0.5VCMOS+0.6V b. Effective setup becomes tS4 ' =tS4+[PDNXA*64*t SCYCLE+tPDNXB,MAX]-[PDNX*256*t if [PDNX*256*t SCYCLE] < [PDNXA*64*t SCYCLE+tPDNXB,MAX]. See Figure 48. SCYCLE] Page 45 Rev. 0.9 July 1999 KM416RD8AS Electrical Characteristics Table 20: Electrical Characteristics Symbol JC IREF IOH IALL IOL rOUT II,CMOS VOL,CMOS VOH,CMOS Parameter and Conditions Junction-to-Case thermal resistance VREF current @ VREF,MAX RSL output high current @ (0VOUTVDD) RSL IOL current @ VOL = 0.9V, RSL IOL current resolution step Dynamic output impedance CMOS input leakage current @ (0VI,CMOSVCMOS) CMOS output voltage @ IOL,CMOS= 1.0mA CMOS output high voltage @ IOH,CMOS = -0.25mA VDD,MIN , TJ,MAXa -10 -10 22 100 -10.0 VCMOS-0.3 Min Target Direct RDRAMTM Max TBD 10 10 50 2.0 10.0 0.3 - Unit C/Watt A A mA mA A V V a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current. Timing Characteristics Table 21: Timing Characteristics Symbol tQ tQR, tQF tQ1 tQR1, tQF1 tPROP1 tNAPXA tNAPXB tPDNXA tPDNXB tAS tSA tASN tASP Parameter CTM-to-DQA/DQB output time DQA/DQB output rise and fall times SCK-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read packet). SIOOUT rise/fall @ C LOAD,MAX = 20pF SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF NAP exit delay - phase A NAP exit delay - phase B PDN exit delay - phase A PDN exit delay - phase B ATTN-to-STBY power state delay STBY-to-ATTN power state delay ATTN/STBY-to-NAP power state delay ATTN/STBY-to-PDN power state delay @ tCYCLE=2.5ns Min -0.310 0.2 Max +0.310 0.45 10 5 10 50 40 4 9000 1 0 8 8 Unit ns ns ns ns ns ns ns s tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE Figure(s) Figure 55 Figure 55 Figure 58 Figure 58 Figure 58 Figure 48 Figure 48 Figure 48 Figure 48 Figure 46 Figure 46 Figure 47 Figure 47 Page 46 Rev. 0.9July 1999 KM416RD8AS RSL - Clocking Figure 53 is a timing diagram which shows the detailed requirements for the RSL clock signals on the Channel. The CTM and CTMN are differential clock inputs used for transmitting information on the DQA and DQB, outputs. tCYCLE tCL CTM tCH tCR Target Direct RDRAMTM Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CTM edge to the falling CTM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CTM. The t CR and tCF rise- and fall-time parameters are measured at the 20% and 80% points. tCR VCIH 80% VXVCM VX+ 20% CTMN tCF tTR CFM tCR tCF tCR VCIH 80% VXVCM VX+ 20% CFMN tCF tCL tCYCLE tCH tCF VCIL 50% VCIL 50% Figure 53: RSL Timing - Clock Signals The CFM and CFMN are differential clock outputs used for receiving information on the DQA, DQB, ROW and COL outputs. Most timing is measured relative to the points where they cross. The tCYCLE parameter is measured from the falling CFM edge to the falling CFM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling edges of CFM. The tCR and tCF rise- and fall-time parameters are measured at the 20% and 80% points. The tTR parameter specifies the phase difference that may be tolerated with respect to the CTM and CFM differential clock inputs (the CTM pair is always earlier). Page 47 Rev. 0.9 July 1999 KM416RD8AS RSL - Receive Timing Figure 54 is a timing diagram which shows the detailed requirements for the RSL input signals on the Channel. The DQA, DQB, ROW, and COL signals are inputs which receive information transmitted by a Direct RAC on the Channel. Each signal is sampled twice per tCYCLE interval. Target Direct RDRAMTM The set/hold window of the sample points is tS/tH. The sample points are centered at the 0% and 50% points of a cycle, measured relative to the crossing points of the falling CFM clock edge. The set and hold parameters are measured at the V REF voltage point of the input transition. The tDR and tDF rise- and fall-time parameters are measured at the 20% and 80% points of the input transition. CFM VCIH 80% VXVCM VX+ 20% 50% CFMN VCIL DQA DQB ROW COL tDR tS tH 0.5*t CYCLE tS tH VDIH 80% even odd VREF 20% VDIL tDF Figure 54: RSL Timing - Data Signals for Receive Page 48 Rev. 0.9July 1999 KM416RD8AS RSL - Transmit Timing Figure 55 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel. The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel. Each signal is driven twice per tCYCLE interval. The beginning and end of the even transmit window is at the 75% point of the previous cycle and at the 25% point of the current cycle. The beginning and end of the odd transmit window is at the Target Direct RDRAMTM 25% point and at the 75% point of the current cycle. These transmit points are measured relative to the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal tCYCLE/2, as indicated by the non-zero values of t Q,MIN and tQ,MAX. The tQ parameters are measured at the VREF voltage point of the output transition. The tQR and tQF rise- and fall-time parameters are measured at the 20% and 80% points of the output transition. CTM VCIH 80% VXVCM VX+ 20% 50% CTMN VCIL 0.75*t CYCLE 0.25*t CYCLE tQ,MAX tQ,MIN 0.75*t CYCLE tQ,MAX tQ,MIN VQH 80% even odd 50% DQA DQB tQR 20% VQL tQF Figure 55: RSL Timing - Data Signals for Transmit Page 49 Rev. 0.9 July 1999 KM416RD8AS CMOS - Receive Timing Figure 56 is a timing diagram which shows the detailed requirements for the CMOS input signals . The CMD and SIO0 signals are inputs which receive information transmitted by a controller (or by another RDRAM's SIO1 output. SCK is the CMOS clock signal driven by the controller. All signals are high true. The cycle time, high phase time, and low phase time of the SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the tDR2 SCK Target Direct RDRAMTM 50% level. The rise and fall times of SCK, CMD, and SIO0 are tDR1 and tDF1, measured at the 20% and 80% levels. The CMD signal is sampled twice per t CYCLE1 interval, on the rising edge (odd data) and the falling edge (even data). The set/hold window of the sample points is tS1/tH1. The SCK and CMD timing points are measured at the 50% level. The SIO0 signal is sampled once per t CYCLE1 interval on the falling edge. The set/hold window of the sample points is tS2/tH2. The SCK and SIO0 timing points are measured at the 50% level. VIH,CMOS 80% 50% 20% tCYCLE1 tDF2 tDR2 CMD even odd 50% tCH1 tS1 tH1 tCL1 tS1 tH1 VIH,CMOS 80% VIL,CMOS 20% tDF2 tDR1 SIO0 tS2 tH2 VIH,CMOS 80% VIL,CMOS 50% 20% tDF1 VIL,CMOS Figure 56: CMOS Timing - Data Signals for Receive Page 50 Rev. 0.9July 1999 KM416RD8AS The SCK clock is also used for sampling data on RSL inputs in one situation. Figure 48 shows the PDN and NAP exit sequences. If the PSX field of the INIT register is one (see Figure 27), then the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. Target Direct RDRAMTM only one RDRAM that is in PDN or NAP will perform the exit sequence. The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window tS3/tH3 around the rising edge of SCK. This is shown in Figure 57. The SCK timing point is measured at the 50% level, and the DQA[5:0] bus signals are measured at the V REF level. VIH,CMOS 80% SCK 50% 20% VIL,CMOS tS3 DQA[5:0] PDEV VREF tH3 VDIH 80% 20% VDIL Figure 57: CMOS Timing - Device Address for NAP or PDN Exit Page 51 Rev. 0.9 July 1999 KM416RD8AS CMOS - Transmit Timing Figure 58 is a timing diagram which shows the detailed requirements for the CMOS output signals. The SIO0 signal is driven once per tCYCLE1 interval on the falling edge. The Target Direct RDRAMTM clock-to-output window is t Q1,MIN/tQ1,MAX. The SCK and SIO0 timing points are measured at the 50% level. The rise and fall times of SIO0 are tQR1 and tQF1, measured at the 20% and 80% levels. SCK VIH,CMOS 80% 50% 20% tQ1,MAX tQ1,MIN tQR1 SIO0 VOH,CMOS 80% VIL,CMOS 50% 20% tQF1 tDR1 SIO0 or SIO1 VIH,CMOS 80% VOL,CMOS 50% 20% tDF1 SIO1 or SIO0 tPROP1,MAX tPROP1,MIN VIL,CMOS tQR1 VOH,CMOS 80% 50% 20% tQF1 VOL,CMOS Figure 58: CMOS Timing - Data Signals for Transmit Page 52 Rev. 0.9July 1999 KM416RD8AS Figure 58 also shows the combinational path connecting SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read data only). The tPROP1 parameter specified this propagation delay. The rise and fall times of SIO0 and SIO1 inputs must be tDR1 and tDF1, measured at the 20% and 80% levels. The rise and fall times of SIO0 and SIO1 outputs are tQR1 and tQF1, measured at the 20% and 80% levels. Target Direct RDRAMTM the delay between a RD command packet and read data packet varies as a function of the tTR value. Figure 59 shows this timing for five distinct values of tTR. Case A (t TR=0) is what has been used throughout this document. The delay between the RD command and read data is tCAC. As tTR varies from zero to tCYCLE (cases A through E), the command to data delay is (t CAC-tTR). When the tTR value is in the range 0 to t DCW,MAX, the command to data delay can also be (t CAC-tTR-tCYCLE). This is shown as cases A' and B' (the gray packets). Similarly, when the t TR value is in the range (tCYCLE+tDCW,MIN) to tCYCLE, the command to data delay can also be (tCAC-tTR+tCYCLE). This is shown as cases D' and E' (the gray packets). The RDRAM will work reliably with either the white or gray packet timing. The delay value is selected at initialization, and remains fixed thereafter. RSL - Domain Crossing Window When read data is returned by the RDRAM, imformation must cross from the receive clock domain (CFM) to the transmit clock domain (CTM). The tTR parameter permits the CFM to CTM phase to vary through an entire cycle; i.e. there is no restriction on the alignment of these two clocks. A second parameter tDCW is needed in order to describe how CFM COL RD a1 *** tCYCLE *** tTR Case A Case A' tTR=0 tTR=0 *** tTR Case B Case B' tTR=tDCW,MAX tTR=tDCW,MAX *** tTR Case C tTR=0.5*t CYCLE *** tTR Case D tTR=tCYCLE+tDCW,MIN tCAC-tTR tCAC-tTR+tCYCLE *** tTR Case E Case E' tTR=tCYCLE tTR=tCYCLE tCAC-tTR tCAC-tTR+tCYCLE Q(a1) Q(a1) Q(a1) Q(a1) tCAC-tTR Q(a1) tCAC-tTR tCAC-tTR-tCYCLE Q(a1) Q(a1) tCAC-tTR tCAC -tTR-tCYCLE Q(a1) Q(a1) CTM DQA/B DQA/B CTM DQA/B DQA/B CTM DQA/B CTM DQA/B DQA/B Case D' tTR=tCYCLE+tDCW,MIN CTM DQA/B DQA/B Figure 59: RSL Transmit - Crossing Read Domains Page 53 Rev. 0.9 July 1999 KM416RD8AS Timing Parameters Table 22: Timing Parameter Summary Parameter Description Min -40 -800 Max Units Target Direct RDRAMTM Figure(s) tRC tRAS Row Cycle time of RDRAM banks -the interval between ROWA packets with 28 ACT commands to the same bank. RAS-asserted time of RDRAM bank - the interval between ROWA packet with ACT command and next ROWR packet with PRERa command to the same bank. Row Precharge time of RDRAM banks - the interval between ROWR packet with PRERa command and next ROWA packet with ACT command to the same bank. 20 64sb tCYCLE tCYCLE Figure 15 Figure 16 Figure 15 Figure 16 Figure 15 Figure 16 Figure 12 Figure 13 Figure 15 Figure 16 tRP 8 - tCYCLE tPP tRR tRCD Precharge-to-precharge time of RDRAM device - the interval between succes- 8 sive ROWR packets with PRERa commands to any banks of the same device. RAS-to-RAS time of RDRAM device - the interval between successive ROWA packets with ACT commands to any banks of the same device. 8 - tCYCLE tCYCLE tCYCLE RAS-to-CAS Delay - the interval from ROWA packet with ACT command to 8 COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen by the RDRAM core (tRCD-C ) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface. CAS Access delay - the interval from RD command to Q read data. The equa- 8 tion for tCAC is given in the TPARM register in Figure 39. CAS Write Delay (interval from WR command to D write data. CAS-to-CAS time of RDRAM bank - the interval between successive COLC commands). Length of ROWA, ROWR, COLC, COLM or COLX packet. 6 4 4 tCAC tCWD tCC tPACKET tRTR tOFFP 12 6 4 4 tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE tCYCLE Figure 4 Figure 39 Figure 4 Figure 15 Figure 16 Figure 3 Figure 17 Figure 14 Figure 39 Interval from COLC packet with WR command to COLC packet which causes 8 retire, and to COLM packet with bytemask. The interval (offset) from COLC packet with RDA command, or from COLC 4 packet with retire command (after WRA automatic precharge), or from COLC packet with PREC command, or from COLX packet with PREX command to the equivalent ROWR packet with PRER. The equation for tOFFP is given in the TPARM register in Figure 39. Interval from last COLC packet with RD command to ROWR packet with PRER. Interval from last COLC packet with automatic retire command to ROWR packet with PRER. 4 4 tRDP tRTP - tCYCLE tCYCLE Figure 15 Figure 16 a. Or equivalent PREC or PREX command. See Figure 14. b. This is a constraint imposed by the core, and is therefore in units of s rather than tCYCLE. Page 54 Rev. 0.9July 1999 KM416RD8AS Absolute Maximum Ratings Table 23: Absolute Maximum Ratings Symbol VI,ABS VDD,ABS, VDDA,ABS TSTORE Target Direct RDRAMTM Parameter Voltage applied to any RSL or CMOS pin with respect to Gnd Voltage on VDD and VDDA with respect to Gnd Storage temperature Min - 0.3 - 0.5 - 50 Max VDD+0.3 VDD+1.0 100 Unit V V C IDD - Supply Current Profile Table 24: Supply Current Profile I DD value IDD,PDN IDD,PDN,L IDD,NAP IDD,STBY IDD,ATTN IDD,ATTN-W IDD,ATTN-R RDRAM blocks consuming power @ tCYCLE=2.5nsa Self-refresh only for INIT.LSR=0 Self-refresh only for INIT.LSR= 1 T/RCLK-Nap T/RCLK, ROW-demux T/RCLK, ROW-demux, COL-demux T/RCLK, ROW-demux,COL-demux,DQ-demux,1*WR-SenseAmp,4*ACT-Bank T/RCLK, ROW-demux,COL-demux,DQ-mux,1*RD-SenseAmp,4*ACT-Bank b Min TBD TBD TBD TBD TBD TBD TBD Max 300 4.0 6.0 120 180 575 490 Unit A mA mA mA mA mA mA a. The CMOS interface consumes power in all power states. b. This does not include the IOL sink current. The RDRAM dissipates IOL * VOL in each output driver when a logic one is driven. Page 55 Rev. 0.9 July 1999 KM416RD8AS Capacitance and Inductance Figure 60 shows the equivalent load circuit of the RSL and CMOS pins. The circuit models the load that the device presents to the Channel. Target Direct RDRAMTM Pad LI DQA,DQB,RQ Pin CI RI Gnd Pin Pad LI CTM,CTMN, CFM,CFMN Pin CI RI Gnd Pin Pad LI,CMOS SCK,CMD Pin CI,CMOS Gnd Pin Pad LI,CMOS SIO0,SIO1 Pin CI,CMOS,SIO Gnd Pin Figure 60: Equivalent Load Circuit for RSL Pins Page 56 Rev. 0.9July 1999 KM416RD8AS This circuit does not include pin coupling effects that are often present in the packaged device. Because coupling effects make the effective single-pin inductance LI, and capacitance CI, a function of neighboring pins, these parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel, the effective LI and CI are defined as the worst-case values over all specified operating conditions. LI is defined as the effective pin inductance based on the device pin assignment. Because the pad assignment places Table 25: RSL Pin Parasitics Symbol LI L12 Parameter and Conditions - RSL pins RSL effective input inductance Mutual inductance between any DQA or DQB RSL signals. Mutual inductance between any ROW or COL RSL signals. LI CI C12 CI RI Difference in LI value between average of CTM/CFM and any RSL pins of a single device. RSL effective input capacitance a Mutual capacitance between any RSL signals. Difference in C I value between average of CTM/CFM and any RSL pins of a single device. RSL effective input resistance Min Target Direct RDRAMTM each RSL signal adjacent to an AC ground (a Gnd or Vdd pin), the effective inductance must be defined based on this configuration. Therefore, LI assumes a loop with the RSL pin adjacent to an AC ground. CI is defined as the effective pin capacitance based on the device pin assignment. It is the sum of the effective package pin capacitance and the IO pad capacitance. Max 4.5 0.2 0.6 2.0 nH nH nH nH Unit 2.0 - 2.6 0.1 0.12 pF pF pF 4 18 a. This value is a combination of the device IO circuitry and package capacitances. Table 26: CMOS Pin Parasitics Symbol LI ,CMOS CI ,CMOS CI ,CMOS,SIO Parameter and Conditions - CMOS pins CMOS effective input inductance CMOS effective input capacitance (SCK,CMD)a 1.7 Min 8.0 2.1 7.0 Max nH pF pF Unit CMOS effective input capacitance (SIO1, SIO0) a a. This value is a combination of the device IO circuitry and package capacitances. Page 57 Rev. 0.9 July 1999 KM416RD8AS Center-Bonded uBGA Package Figure 61 shows the form and dimensions of the recommended package for the center-bonded CSP device class. D A B C D E F G H J Top Top 7 6 5 4 3 2 1 d E1 e1 E e2 A Target Direct RDRAMTM Bottom Bottom Figure 61: Center-Bonded uBGA Package Table 27 lists the numerical values corresponding to dimensions shown in Figure 61. Table 27: Center-Bonded uBGA Package Dimensions Symbol e1 e2 A D E E1 d Parameter Ball pitch (x-axis) Ball pitch (y-axis) Package body length Package body width Package total thickness Ball height Ball diameter 1.27 1.27 11.9 11.7 0.45 0.55 Min 1.27 1.27 12.1 11.9 1.25 0.55 0.65 Max Unit mm mm mm mm mm mm mm Page 58 Rev. 0.9July 1999 KM416RD8AS Glossary of Terms ACT activate adjacent ASYM ATTN ATTNR ATTNW AV bank BC BBIT broadcast BR bubble BYT BX C CAL CBIT CCA CCB CFM,CFMN Channel CLRR CMD CNFGA CNFGB COL COL COLC COLM column command COLX controller Target Direct RDRAMTM A logic-device which drives the ROW/COL /DQ wires for a Channel of RDRAMs. Column opcode field in COLC packet. The banks and sense amps of an RDRAM. Clock pins for transmitting packets. IOL value of RSL output drivers. D DBL DC device Activate command from AV field. To access a row and place in sense amp. Two RDRAM banks which share sense amps (also called doubled banks). CCA register field for RSL VOL/VOH. Power state - ready for ROW/COL packets. Power state - transmitting Q packets. Power state - receiving D packets. Opcode field in ROW packets. A block of core of the RDRAM. 2RBIT*2 CBITstorage cells in the COP core CTM,CTMN current control Periodic operations to update the proper Write data packet on DQ pins. CNFGB register field - doubled-bank. Device address field in COLC packet. An RDRAM on a Channel. Control register with device address that is matched against DR, DC, and DX fields. Device match for ROW packet decode. DQA and DQB pins. Pins for data byte A. Pins for data byte B. NAPX register field - PDN/NAP exit. fields in ROWA and ROWR packets. DEVID DM Bank address field in COLC packet. CNFGA register field - # bank address bits. An operation executed by all RDRAMs. Bank address field in ROW packets. Idle cycle(s) on RDRAM pins needed because of a resource constraint. CNFGB register field - 8/9 bits per byte. Bank address field in COLX packet. Column address field in COLC packet. Calibrate (IOL) command in XOP field. CNFGB register field - # column address bits. Control register - current control A. Control register - current control B. Clock pins for receiving packets. ROW/COL/DQ pins and external wires. Clear reset command from SOP field. CMOS pin for initialization/power control. Control register with configuration fields. Control register with configuration fields. Pins for column-access control. COLC,COLM,COLX packet on COL pins. Column operation packet on COL pins. Write mask packet on COL pins. Rows in a bank or activated row in sense amps have 2CBIT dualocts column storage. A decoded bit-combination from a field. Extended operation packet on COL pins. doubled-bank RDRAM with shared sense amp. DQ DQA DQB DQS DR,DR4T,DR4F Device address field and packet framing dualoct DX field INIT initialization LSR M MA MB MSK MVER NAP NAPR NAPRC NAPXA NAPXB NOCOP NOROP 16 bytes - the smallest addressable datum. Device address field in COLX packet. A collection of bits in a packet. Control register with initialization fields. Configuring a Channel of RDRAMs so they are ready to respond to transactions. CNFGA register field - low-power selfrefresh. Mask opcode field (COLM/COLX packet). Field in COLM packet for masking byte A. Field in COLM packet for masking byte B. Mask command in M field. Control register - manufacturer ID. Power state - needs SCK/CMD wakeup. Nap command in ROP field. Conditional nap command in ROP field. NAPX register field - NAP exit delay A. NAPX register field - NAP exit delay B. No-operation command in COP field. No-operation command in ROP field. Page 59 Rev. 0.9 July 1999 KM416RD8AS NOXOP NSR packet PDN PDNR PDNXA PDNXB Target Direct RDRAMTM ROWR RQ RSL SAM SA SBC SCK SD SDEV SDEVID self-refresh sense amp SETF SETR SINT SIO0,SIO1 SOP SRD SRP SRQ STBY SVER SWR TCAS TCLS TCLSCAS TCYCLE TDAC TEST77 TEST78 TRDLY transaction transmit WR/WRA write XOP No-operation command in XOP field. INIT register field- NAP self-refresh. A collection of bits carried on the Channel. Power state - needs SCK/CMD wakeup. Powerdown command in ROP field. Control register - PDN exit delay A. Control register - PDN exit delay B. PREC,PRER,PREX precharge commands. Precharge command in COP field. Prepares sense amp and bank for activate. Precharge command in ROP field. Precharge command in XOP field. INIT register field - PDN/NAP exit. INIT register field - PDN self-refresh. CNFGB register field - protocol version. Read data packet on DQ pins. Row address field of ROWA packet. CNFGB register field - # row address bits. Read (/precharge) command in COP field. Operation of accesssing sense amp data. Moving information from the Channel into the RDRAM (a serial stream is demuxed). Refresh-activate command in ROP field. Control register - next bank (self-refresh). CNFGA register field - ignore bank bits (for REFA and self-refresh). Refresh-precharge command in ROP field. Control register - next row for REFA. Periodic operations to restore storage cells. The automatic operation that stores write buffer into sense amp after WR command. RLXC,RLXR,RLXX relax commands. Relax command in COP field. Relax command in ROP field. Relax command in XOP field. Row-opcode field in ROWR packet. 2CBIT dualocts of cells (bank/sense amp). Pins for row-access control ROWA or ROWR packets on ROW pins. Activate packet on ROW pins. Row operation packet on ROW pins. Alternate name for ROW/COL pins. Rambus Signaling Levels. Sample (IOL) command in XOP field. Serial address packet for control register transactions w/ SA address field. Serial broadcast field in SRQ. CMOS clock pin.. Serial data packet for control register transactions w/ SD data field. Serial device address in SRQ packet. INIT register field - Serial device ID. Refresh mode for PDN and NAP. Fast storage that holds copy of bank's row. Set fast clock command from SOP field. Set reset command from SOP field. Serial interval packet for control register read/write transactions. CMOS serial pins for control registers. Serial opcode field in SRQ. Serial read opcode command from SOP. INIT register field - Serial repeat bit. Serial request packet for control register read/write transactions. Power state - ready for ROW packets. Control register - stepping version. Serial write opcode command from SOP. TCLSCAS register field - t CAS core delay. TCLSCAS register field - t CLS core delay. Control register - tCAS and tCLS delays. Control register - tCYCLE delay. Control register - tDAC delay. Control register - for test purposes. Control register - for test purposes. Control register - tRDLY delay. ROW,COL,DQ packets for memory access. Moving information from the RDRAM onto the Channel (parallel word is muxed). Write (/precharge) command in COP field. Operation of modifying sense amp data. Extended opcode field in COLX packet pin efficiency The fraction of non-idle cycles on a pin. PRE PREC precharge PRER PREX PSX PSR PVER Q R RBIT RD/RDA read receive REFA REFB REFBIT REFP REFR refresh retire RLX RLXC RLXR RLXX ROP row ROW ROW ROWA Page 60 Rev. 0.9July 1999 KM416RD8AS Table Of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key Timing Parameters/Part Numbers . . . . . . . . . . . 1 Pinouts and Definitions . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6,7 Field Encoding Summary . . . . . . . . . . . . . . . . . . . . .8,9 DQ Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10 COLM Packet to D Packet Mapping . . . . . . . . . .10,11 ROW-to-ROW Packet Interaction . . . . . . . . . . . 12, 13 ROW-to-COL Packet Interaction . . . . . . . . . . . . . . . 13 COL-to-COL Packet Interaction . . . . . . . . . . . . . . . . 14 COL-to-ROW Packet Interaction . . . . . . . . . . . . . . . 15 ROW-to-ROW Examples . . . . . . . . . . . . . . . . . . .16,17 Row and Column Cycle Description . . . . . . . . . . . . 17 Precharge Mechanisms . . . . . . . . . . . . . . . . . . . .18,19 Read Transaction - Example . . . . . . . . . . . . . . . . . . 20 Write Transaction - Example . . . . . . . . . . . . . . . . . . 21 Write/Retire - Examples . . . . . . . . . . . . . . . . . . . 22, 23 Interleaved Write - Example. . . . . . . . . . . . . . . . . . . 24 Interleaved Read - Example . . . . . . . . . . . . . . . . . . 25 Interleaved RRWW . . . . . . . . . . . . . . . . . . . . . . . . . 25 Control Register Transactions . . . . . . . . . . . . . . . . . 26 Control Register Packets . . . . . . . . . . . . . . . . . . . . . 27 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-29 Control Register Summary. . . . . . . . . . . . . . . . . 30-37 Power State Management . . . . . . . . . . . . . . . . . 38-41 Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Current and Temperature Control . . . . . . . . . . . . . . 43 Electrical Conditions . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Conditions . . . . . . . . . . . . . . . . . . . . . . . .44-45 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 46 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 46 RSL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RSL - Receive Timing . . . . . . . . . . . . . . . . . . . . . . . 48 RSL - Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . 49 CMOS - Receive Timing . . . . . . . . . . . . . . . . . . .50-51 CMOS - Transmit Timing . . . . . . . . . . . . . . . . . . .52-53 RSL - Domain Crossing Window . . . . . . . . . . . . . . . 53 Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 54 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 55 IDD - Supply Current Profile . . . . . . . . . . . . . . . . . . 55 Target Direct RDRAMTM Capacitance and Inductance . . . . . . . . . . . . . . . .56-57 Edge-Bonded mBGA Package . . . . . . . . . . . . . . . . 58 Edge-Bonded mBGA Package . . . . . . . . . . . . . . . . 59 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . .60-61 (c) Copyright July 1999 Samsung Electronics. All rights reserved. Direct Rambus and Direct RDRAM are trademarks of Rambus Inc. Rambus, RDRAM, and the Rambus Logo are registered trademarks of Rambus Inc. This document contains advanced information that is subject to change by Samsung without notice. Document Version 0.9 Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Kiheung-Eup Yongin-City Kyunggi-Do, KOREA Telephone: 82-331-209-4519 Fax: 82-2-760-7990 http://www.samsungsemi.com Page 61 Rev. 0.9 July 1999 |
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